Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
BJ

Brian L. Ji — 45 Patents

IBM: 42 patents #2,200 of 70,183Top 4%
CGCummins Power Generation: 2 patents #88 of 278Top 35%
HLHefechip Corporation Limited: 1 patents #11 of 16Top 70%
Infineon Technologies Ag: 1 patents #168 of 446Top 40%
Mount Kisco, NY: #11 of 232 inventorsTop 5%
New York: #2,204 of 115,490 inventorsTop 2%
Overall (All Time): #64,229 of 4,157,543Top 2%
45 Patents All Time

Issued Patents All Time

Showing 26–45 of 45 patents

Patent #TitleCo-InventorsDate
7460389 Write operations for phase-change-material memory Louis Hsu, Chung H. Lam 2008-12-02
7438822 Apparatus and method for shielding a wafer from charged particles during plasma etching Hongwen Yan, Siddhartha Panda, Richard S. Wise, Bomy Chen 2008-10-21
7409019 High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion Louis C. Hsu, James S. Mason, Karl D. Selander, Michael A. Sorna, Steven J. Zier 2008-08-05
7378895 On-chip electrically alterable resistor Louis C. Hsu, Chung H. Lam 2008-05-27
7355872 Segmented content addressable memory architecture for improved cycle time and reduced power consumption Louis L. Hsu, Li-Kong Wang 2008-04-08
7342406 Methods and apparatus for inline variability measurement of integrated circuit components Manjul Bhushan, Karen Gettings, Wilfried E. Haensch, Mark B. Ketchen 2008-03-11
7319608 Non-volatile content addressable memory using phase-change-material memory elements Louis Hsu, Chung H. Lam, Hon-Sum Philip Wong 2008-01-15
7233177 Precision tuning of a phase-change resistive element Louis C. Hsu, Chung H. Lam 2007-06-19
7216284 Content addressable memory having reduced power consumption Louis L. Hsu, Li-Kong Wang 2007-05-08
7203794 Destructive-read random access memory system buffered with destructive-read memory cache Chorng-Lii Hwang, Toshiaki Kirihata, Seiji Munetoh 2007-04-10
7005319 Global planarization of wafer scale package with precision die thickness control Howard H. Chen, Louis L. Hsu 2006-02-28
6980824 Method and system for optimizing transmission and reception power levels in a communication system Louis L. Hsu, Karl D. Selander, Michael A. Sorna 2005-12-27
6975140 Adaptive data transmitter having rewriteable non-volatile storage Louis Hsu, William F. Washburn 2005-12-13
6948028 Destructive-read random access memory system buffered with destructive-read memory cache Chorng-Lii Hwang, Toshiaki Kirihata, Seiji Munetoh 2005-09-20
6823293 Hierarchical power supply noise monitoring device and system for very large scale integrated circuits Howard H. Chen, Louis L. Hsu, Li-Kong Wang 2004-11-23
6801980 Destructive-read random access memory system buffered with destructive-read memory cache Chorng-Lii Hwang, Toshiaki Kirihata, Seiji Munetoh 2004-10-05
6477630 Hierarchical row activation method for banking control in multi-bank DRAM Toshiaki Kirihata, Dmitry Netis 2002-11-05
6400639 Wordline decoder system and method Toshiaki Kirihata, Dmitry Netis 2002-06-04
6252806 Multi-generator, partial array Vt tracking system to improve array retention time Wayne F. Ellis, Louis Hsu, Yujon Li, Oliver Weinfurtner 2001-06-26
6081479 Hierarchical prefetch for semiconductor memories Toshiaki Kirihata, Gerhard Mueller, David R. Hanson 2000-06-27