Issued Patents All Time
Showing 26–50 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8751655 | Collective acceleration unit tree structure | Lakshminarayana B. Arimilli, Paul Frank Lecocq, Hanhong Xue | 2014-06-10 |
| 8417778 | Collective acceleration unit tree flow control and retransmit | Lakshminarayana B. Arimilli, Jody B. Joyner, Paul Frank Lecocq, Hanhong Xue | 2013-04-09 |
| 8302109 | Synchronization optimized queuing system | Lakshminarayana B. Arimilli, Claude Basso, Piyush Chaudhary, Jody B. Joyner, Jan-Bernd Themann +2 more | 2012-10-30 |
| 8281075 | Processor system and methods of triggering a block move using a system bus write command initiated by user code | Lakshminarayana B. Arimilli, Brian Mitchell Bass, David W. Cummings, Guy L. Guthrie, Ronald Nick Kalla +4 more | 2012-10-02 |
| 8266386 | Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocols | — | 2012-09-11 |
| 8131906 | Voltage indicator signal generation system and method | Parag Birmiwal | 2012-03-06 |
| 8108618 | Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocols | — | 2012-01-31 |
| 8095720 | Voltage indicator signal generation system and method | Parag Birmiwal | 2012-01-10 |
| 8077602 | Performing dynamic request routing based on broadcast queue depths | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2011-12-13 |
| 7996614 | Cache intervention on a separate data bus when on-chip bus has separate read and write data busses | Robert M. Dinkjian | 2011-08-09 |
| 7987437 | Structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization | Richard Nicholas | 2011-07-26 |
| 7934042 | Voltage indicator signal generation system and method | Parag Birmiwal | 2011-04-26 |
| 7921316 | Cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2011-04-05 |
| 7882278 | Utilizing programmable channels for allocation of buffer space and transaction control in data communications | Sundeep Chadha, Mark A. Check, Michael Grassi | 2011-02-01 |
| 7865644 | Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining | Richard Nicholas, Prasanna Srinivasan | 2011-01-04 |
| 7827428 | System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2010-11-02 |
| 7779148 | Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2010-08-17 |
| 7725660 | Directory for multi-node coherent bus | Gary Dale Carpenter, Scott Douglas Clark, Russell D. Hoover, Charles Ray Johns, David J. Krolak +2 more | 2010-05-25 |
| 7707347 | Data path master/slave data processing device apparatus | Richard Siegmund, Jr., Barry Joe Wolford | 2010-04-27 |
| 7685373 | Selective snooping by snoop masters to locate updated data | James Norris Dieffenderfer, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier +1 more | 2010-03-23 |
| 7669013 | Directory for multi-node coherent bus | Gary Dale Carpenter, Scott Douglas Clark, Russell D. Hoover, Charles Ray Johns, David J. Krolak +2 more | 2010-02-23 |
| 7668996 | Method of piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization | Richard Nicholas | 2010-02-23 |
| 7647435 | Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism | Mark A. Check, Michael Grassi | 2010-01-12 |
| 7620749 | Descriptor prefetch mechanism for high latency and out of order DMA device | Giora Biran, Luis de la Torre, Jyoti Gupta, Richard Nicholas | 2009-11-17 |
| 7603490 | Barrier and interrupt mechanism for high latency and out of order DMA device | Giora Biran, Luis de la Torre, Jyoti Gupta, Richard Nicholas | 2009-10-13 |