Issued Patents All Time
Showing 726–750 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9899274 | Low-cost SOI FinFET technology | Stephen W. Bedell, Joel P. de Souza, Devendra K. Sadana, Dominic J. Schepis | 2018-02-20 |
| 9893207 | Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2018-02-13 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-02-13 |
| 9893014 | Designable channel FinFET fuse | Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki | 2018-02-13 |
| 9892978 | Forming a CMOS with dual strained channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2018-02-13 |
| 9892975 | Adjacent strained <100> NFET fins and <110> PFET fins | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi | 2018-02-13 |
| 9892925 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Kangguo Cheng, Pouya Hashemi, Shogo Mochizuki | 2018-02-13 |
| 9887197 | Structure containing first and second vertically stacked nanosheets having different crystallographic orientations | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-02-06 |
| 9881798 | Metal cap integration by local alloying | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-01-30 |
| 9876075 | Method of forming dielectric with air gaps for use in semiconductor devices | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-01-23 |
| 9876015 | Tight pitch inverter using vertical transistors | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-01-23 |
| 9875939 | Methods of forming uniform and pitch independent fin recess | Yue Ke, Benjamin G. Moser, Dominic J. Schepis, Melissa A. Smith, Henry K. Utomo +2 more | 2018-01-23 |
| 9875896 | Method for forming a strained semiconductor layer including replacing an etchable material formed under the strained semiconductor layer with a dielectric layer | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-01-23 |
| 9871140 | Dual strained nanosheet CMOS and methods for fabricating | Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi | 2018-01-16 |
| 9870953 | System on chip material co-integration | Takashi Ando, Lukas Czornomaz, Pouya Hashemi | 2018-01-16 |
| 9865737 | Formation of FinFET junction | Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott | 2018-01-09 |
| 9865714 | III-V lateral bipolar junction transistor | Pouya Hashemi, Tak H. Ning | 2018-01-09 |
| 9865587 | Method and structure for forming buried ESD with FinFETs | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2018-01-09 |
| 9865538 | Metallic blocking layer for reliable interconnects and contacts | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2018-01-09 |
| 9865511 | Formation of strained fins in a finFET device | Pouya Hashemi, Ali Khakifirooz | 2018-01-09 |
| 9865462 | Strain relaxed buffer layers with virtually defect free regions | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-01-09 |
| 9859369 | Semiconductor device including nanowire transistors with hybrid channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2018-01-02 |
| 9859216 | Voidless contact metal structures | Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki | 2018-01-02 |
| 9859219 | Copper wiring structures with copper titanium encapsulation | Praneet Adusumilli, Oscar van der Straten | 2018-01-02 |
| 9859301 | Methods for forming hybrid vertical transistors | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2018-01-02 |