Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10658322 | High bandwidth memory package for high performance processors | Nam Hoon Kim, Teckgyu Kang | 2020-05-19 |
| 10643913 | Apparatus and mechanisms for reducing warpage and increasing surface mount technology yields in high performance integrated circuit packages | Phillip La, Michael T. Wise | 2020-05-05 |
| 10548239 | Cooling electronic devices in a data center | Madhusudan K. Iyengar, Gregory Sizikov, Yuan Li, Jorge Padilla, Teckgyu Kang | 2020-01-28 |
| 10548240 | Cooling electronic devices in a data center | Madhusudan K. Iyengar, Christopher G. Malone, Yuan Li, Jorge Padilla, Teckgyu Kang +1 more | 2020-01-28 |
| 10515920 | High bandwidth memory package for high performance processors | Nam Hoon Kim, Teckgyu Kang | 2019-12-24 |
| 10468359 | Package stiffener for protecting semiconductor die | William Frank Edwards, Erick Tuttle, Madhusudan K. Iyengar, Yuan Li, Jorge Padilla +1 more | 2019-11-05 |
| 10468351 | Multi-chip silicon substrate-less chip packaging | Suresh Ramalingam | 2019-11-05 |
| 10257921 | Embedded air gap transmission lines | Richard Stuart Roy, Pierre-Luc Cantin, Teckgyu Kang | 2019-04-09 |
| 10083920 | Package stiffener for protecting semiconductor die | William Frank Edwards, Erick Tuttle, Madhusudan K. Iyengar, Yuan Li, Jorge Padilla +1 more | 2018-09-25 |
| 10025047 | Integration of silicon photonics IC for high data rate | Hong Liu, Ryohei Urata, Teckgyu Kang | 2018-07-17 |
| 9966345 | Protective barrier for integrated circuit packages housing a voltage regulator and a load | Gregory Sizikov | 2018-05-08 |
| 9831104 | Techniques for molded underfill for integrated circuit dies | Suresh Ramalingam | 2017-11-28 |
| 9627329 | Interposer with edge reinforcement and method for manufacturing same | Suresh Ramalingam | 2017-04-18 |
| 9508563 | Methods for flip chip stacking | Suresh Ramalingam | 2016-11-29 |
| 9418966 | Semiconductor assembly having bridge module for die-to-die interconnection | Suresh Ramalingam | 2016-08-16 |
| 9245865 | Integrated circuit package with multi-trench structure on flipped substrate contacting underfill | Suresh Ramalingam | 2016-01-26 |
| 9224697 | Multi-die integrated circuits implemented using spacer dies | Suresh Ramalingam | 2015-12-29 |
| 9147661 | Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same | Suresh Ramalingam | 2015-09-29 |
| 9006030 | Warpage management for fan-out mold packaged integrated circuit | Suresh Ramalingam, Paul Ying-Fung Wu, Manoj Nachnani | 2015-04-14 |
| 8946884 | Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product | Suresh Ramalingam, Namhoon Kim, Joong-Ho Kim | 2015-02-03 |
| 8852988 | Semiconductor package and method of manufacturing the same | Hyung-Sun Jang, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim | 2014-10-07 |
| 8618648 | Methods for flip chip stacking | Suresh Ramalingam | 2013-12-31 |
| 8603917 | Method of processing a wafer | Nagarajan Ranganathan | 2013-12-10 |
| 8466527 | Semiconductor package and method of manufacturing the same | Hyung-Sun Jang, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim | 2013-06-18 |
| 8114701 | Camera modules and methods of fabricating the same | Tae-Je Cho, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Hyung-Sun Jang | 2012-02-14 |