Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11963452 | Method of making piezoelectric microphone with deflection control | Jia Jie Xia, Rakesh Kumar, Minu Prabhachandran Nair | 2024-04-16 |
| 11269990 | Detecting threats in big data platforms based on call trace and memory access patterns | Santosh K. Aditham | 2022-03-08 |
| 10886455 | Piezoelectric microphone with deflection control and method of making the same | Jia Jie Xia, Rakesh Kumar, Minu Prabhachandran Nair | 2021-01-05 |
| 10805316 | Systems and methods for detecting attacks in big data systems | Santosh K. Aditham | 2020-10-13 |
| 10678907 | Detecting threats in big data platforms based on call trace and memory access patterns | Santosh K. Aditham | 2020-06-09 |
| 10358340 | Integrated circuits having shielded MEMS devices and methods for fabricating shielded MEMS devices | Humberto Campanella-Pineda, Rakesh Kumar, Zouhair Sbiaa, RAMACHANDRAMURTHY PRADEEP YELEHANKA | 2019-07-23 |
| 9550668 | Integrated MEMS pressure sensor and MEMS inertial sensor | Jia Jie Xia, Rakesh Kumar, Aveek N. Chatterjee | 2017-01-24 |
| 9546090 | Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices | Jia Jie Xia, Rakesh Kumar, Aveek N. Chatterjee | 2017-01-17 |
| 9531384 | Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits | Matthew David Morrison, Jarred Adam Ligatti | 2016-12-27 |
| 8729695 | Wafer level package and a method of forming a wafer level package | Chirayarikathu Veedu Sankarapillai Premachandran, Rakesh Kumar, Won Kyoung Choi, Ebin Liao, Yasuyuki Mitsuoka +2 more | 2014-05-20 |
| 8603917 | Method of processing a wafer | Woon-Seong Kwon | 2013-12-10 |
| 7944230 | Methodology and apparatus for reduction of soft errors in logic circuits | Koustav Bhattacharya | 2011-05-17 |
| 7880496 | Conservative logic gate for design of quantum dot cellular automata circuits | Himanshu Thapliyal | 2011-02-01 |
| 7804320 | Methodology and apparatus for reduction of soft errors in logic circuits | Koustav Bhattacharya | 2010-09-28 |
| 7256608 | Method and apparatus for reducing leakage in integrated circuits | Narender Hanchate | 2007-08-14 |
| 5659362 | VLSI circuit structure for implementing JPEG image compression standard | Mario Kovac | 1997-08-19 |
| 5553272 | VLSI circuit structure for determining the edit distance between strings | Raghu Sastry | 1996-09-03 |
| 5535292 | VLSI architectures for polygon recognition | Raghu Sastry | 1996-07-09 |