Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8334573 | Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices | Maciej Wiatr, Markus Forsberg, Stephan Kronholz | 2012-12-18 |
| 8268679 | Semiconductor device comprising eFUSES of enhanced programming efficiency | Oliver Aubel, Jens Poppe, Andreas Kurz | 2012-09-18 |
| 8193066 | Semiconductor device comprising a silicon/germanium resistor | Andreas Kurz, Christoph Schwan, John Morgan | 2012-06-05 |
| 8097519 | SOI device having a substrate diode formed by reduced implantation energy | Maciej Wiatr, Markus Forsberg | 2012-01-17 |
| 7964458 | Method for forming a strained transistor by stress memorization based on a stressed implantation mask | Frank Wirbeleit, Martin Gerhardt | 2011-06-21 |
| 7923338 | Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence | Maciej Wiatr, Anthony Mowry | 2011-04-12 |
| 7879667 | Blocking pre-amorphization of a gate electrode of a transistor | Anthony Mowry, Markus Lenski, Andy Wei | 2011-02-01 |
| 7763515 | Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate | Andy Wei, Thorsten Kammler, Manfred Horstmann | 2010-07-27 |
| 7569437 | Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern | Frank Wirbeleit, Andy Wei | 2009-08-04 |