Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8334573 | Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices | Markus Forsberg, Stephan Kronholz, Roman Boschke | 2012-12-18 |
| 8298924 | Method for differential spacer removal by wet chemical etch process and device with differential spacer structure | Frank Wirbeleit, Andy Wei, Andreas Gehring | 2012-10-30 |
| 8212184 | Cold temperature control in a semiconductor device | Anthony Mowry, Casey Scott, Ralf Richter | 2012-07-03 |
| 8158482 | Asymmetric transistor devices formed by asymmetric spacers and tilted implantation | Jan Hoentschel, Uwe Griebenow | 2012-04-17 |
| 8124467 | Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors | Stephan Kronholz, Vassilios Papageorgiou | 2012-02-28 |
| 8097519 | SOI device having a substrate diode formed by reduced implantation energy | Markus Forsberg, Roman Boschke | 2012-01-17 |
| 8018260 | Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation | Vassilios Papageorgiou, Jan Hoentschel | 2011-09-13 |
| 7939399 | Semiconductor device having a strained semiconductor alloy concentration profile | Anthony Mowry, Bernhard Trui, Andreas Gehring, Andy Wei | 2011-05-10 |
| 7923338 | Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence | Roman Boschke, Anthony Mowry | 2011-04-12 |
| 7897451 | Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors | Casey Scott, Andreas Gehring, Peter Javorka, Andy Wei | 2011-03-01 |
| 7790537 | Method for creating tensile strain by repeatedly applied stress memorization techniques | Andy Wei, Anthony Mowry, Andreas Gehring | 2010-09-07 |