Issued Patents All Time
Showing 101–125 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8507983 | High voltage device | Guowei Zhang | 2013-08-13 |
| 8492226 | Trench transistor | Shajan Mathew | 2013-07-23 |
| 8450832 | Large tuning range junction varactor | Manju Sarkar | 2013-05-28 |
| 8445960 | Self-aligned body fully isolated device | — | 2013-05-21 |
| 8410553 | Semiconductor structure including high voltage device | Jeoung Mo Koo, Sanford Chu, Chunlin Zhu, Yisuo Li | 2013-04-02 |
| 8334567 | LDMOS using a combination of enhanced dielectric stress layer and dummy gates | Sanford Chu, Yisuo Li, Guowei Zhang | 2012-12-18 |
| 8288235 | Self-aligned body fully isolated device | — | 2012-10-16 |
| 8222130 | High voltage device | Guowei Zhang | 2012-07-17 |
| 8138051 | Integrated circuit system with high voltage transistor and method of manufacture thereof | Yemin Dong, Xin Zou, Chao-Ming Cheng, Shao-fu Sanford Chu | 2012-03-20 |
| 8053319 | Method of forming a high voltage device | Junwen LIU, Yan Jin, Baofu Zhu | 2011-11-08 |
| 7994563 | MOS varactors with large tuning range | Manju Sarkar | 2011-08-09 |
| 7951680 | Integrated circuit system employing an elevated drain | Guowei Zhang, Yisuo Li, Ming-Shuan Li, Shao-fu Sanford Chu | 2011-05-31 |
| 7867862 | Semiconductor structure including high voltage device | Jeoung Mo Koo, Sanford Chu, Chunlin Zhu, Yisuo Li | 2011-01-11 |
| 7846805 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process | Shaoqiang Zhang, Sanford Chu | 2010-12-07 |
| 7824968 | LDMOS using a combination of enhanced dielectric stress layer and dummy gates | Sanford Chu, Yisuo Li, Guowei Zhang | 2010-11-02 |
| 7618873 | MOS varactors with large tuning range | Manju Sarkar | 2009-11-17 |
| 7488662 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process | Shaoqiang Zhang, Sanford Chu | 2009-02-10 |
| 7410874 | Method of integrating triple gate oxide thickness | Sanford Chu, Hwee Ngoh Chua | 2008-08-12 |
| 7382027 | MOSFET device with low gate contact resistance | Sanford Chu, Lap Chan, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zhen Zheng | 2008-06-03 |
| 7326609 | Semiconductor device and fabrication method | Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan +3 more | 2008-02-05 |
| 7323736 | Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits | Pradeep Ramachandramurthy Yelehanka, Sanford Chu, Chit Hwei Ng, Jia Zhen | 2008-01-29 |
| 7268412 | Double polysilicon bipolar transistor | Shao-fu Sanford Chu | 2007-09-11 |
| 7250669 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks | Lap Chan, Sanford Chu, Chit Hwei Ng, Jia Zhen Zheng, Johnny Kok Wai Chew +1 more | 2007-07-31 |
| 7238971 | Self-aligned lateral heterojunction bipolar transistor | Jian Xun Li, Lap Chan, Jia Zhen Zheng, Shao-fu Sanford Chu | 2007-07-03 |
| 7060193 | Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits | Pradeep Ramachandramurthy Yelehanka, Sanford Chu, Chit Hwei Ng, Jia Zhen | 2006-06-13 |