Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7206241 | Semiconductor device and programming method | Kazunari Kido, Yasushi Kasa, Minoru Yamashita, Hiroaki Wada | 2007-04-17 |
| 7180785 | Nonvolatile semiconductor memory device with a plurality of sectors | — | 2007-02-20 |
| 7113442 | Non-volatile semiconductor memory, semiconductor device and charge pump circuit | — | 2006-09-26 |
| 7023897 | Transmission circuit | — | 2006-04-04 |
| 6975543 | Nonvolatile semiconductor memory device which stores two bits per memory cell | — | 2005-12-13 |
| 6944057 | Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference | Edward Franklin Runnion, Tien-Chun Yang, Binh Quang Le, Shigekazu Yamada, Darlene Hamilton +2 more | 2005-09-13 |
| 6937987 | Character information receiving apparatus | — | 2005-08-30 |
| 6885353 | Variable type antenna matching circuit | — | 2005-04-26 |
| 6865133 | Memory circuit with redundant configuration | Yoshihiro Tsukidate, Yasushi Kasa, Tsutomu Nakai, Andy Cheung | 2005-03-08 |
| 6819591 | Method for erasing a memory sector in virtual ground architecture with reduced leakage current | Ming-Huei Shieh, Santosh Yachareni, Pau-Ling Chen | 2004-11-16 |
| 6813189 | System for using a dynamic reference in a double-bit cell memory | — | 2004-11-02 |
| 6813735 | I/O based column redundancy for virtual ground with 2-bit cell flash memory | Pau-Ling Chen | 2004-11-02 |
| 6791880 | Non-volatile memory read circuit with end of life simulation | Binh Quang Le, Pau-Ling Chen, Darlene Hamilton, Edward Hsia | 2004-09-14 |
| 6744666 | Method and system to minimize page programming time for flash memory devices | Santosh Yachareni, Ming-Huei Shieh, Pau-Ling Chen | 2004-06-01 |
| 6731703 | Reception power level calculating circuit and receiver using the same | — | 2004-05-04 |
| 6721370 | Phase correction circuit for radio communication apparatus | — | 2004-04-13 |
| 6713809 | Dual bit memory device with isolated polysilicon floating gates | Jusuke Ogura, Masaru Yano, Hideki Komori, Tuan Pham, Angela T. Hui | 2004-03-30 |
| 6643178 | System for source side sensing | — | 2003-11-04 |
| 6574139 | Method and device for reading dual bit memory cells using multiple reference cells with two side read | — | 2003-06-03 |
| 6525969 | Decoder apparatus and methods for pre-charging bit lines | Santosh Yachareni | 2003-02-25 |
| 6510082 | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | Binh Quang Le, Pau-Ling Chen, Michael A. Van Buskirk, Santosh Yachareni, Michael Chung +1 more | 2003-01-21 |
| 6493266 | Soft program and soft program verify of the core cells in flash memory array | Santosh Yachareni, Darlene Hamilton, Binh Quang Le | 2002-12-10 |
| 6469942 | System for word line boosting | — | 2002-10-22 |
| 6463516 | Variable sector size for a high density flash memory device | Nancy Leong, Johnny C. Chen, Tiao-Hua Kuo | 2002-10-08 |
| 6385093 | I/O partitioning system and methodology to reduce band-to-band tunneling current during erase | Edward V. Bautista, Jr., Feng Pan, Weng Fook Lee, Ravi Sunkavalli, Darlene Hamilton | 2002-05-07 |