Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7611976 | Gate electrode dopant activation method for semiconductor manufacturing | Khaled Ahmed, Kevin Cunningham, Robert C. McIntosh, Abhilash J. Mayur, Haifan Liang +6 more | 2009-11-03 |
| 7602067 | Hetero-structure variable silicon rich nitride for multiple level memory flash memory device | Robert B. Ogle | 2009-10-13 |
| 7390536 | Method for fabricating composite gas separation modules | Ivan P. Mardilovich, Erik Edwin Engwall | 2008-06-24 |
| 7255726 | Composite gas separation modules having high Tamman temperature intermediate layers | Ivan P. Mardilovich, Erik Edwin Engwall | 2007-08-14 |
| 7175694 | Composite gas separation modules having intermediate porous metal layers | Ivan P. Mardilovich, Erik Edwin Engwall | 2007-02-13 |
| 7172644 | Method for curing defects in the fabrication of a composite gas separation module | Ivan P. Mardilovich, Erik Edwin Engwall | 2007-02-06 |
| 7081419 | Gate dielectric structure for reducing boron penetration and current leakage | Yuan-Feng Chen, Feng Li, Kurt G. Steiner | 2006-07-25 |
| 7078302 | Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal | Khaled Ahmed, Kevin Cunningham, Robert C. McIntosh, Abhilash J. Mayur, Haifan Liang +6 more | 2006-07-18 |
| 6940151 | Silicon-rich low thermal budget silicon nitride for integrated circuits | Michael Carroll, Minesh Patel, Peyman Sana | 2005-09-06 |
| 6815302 | Method of making a bipolar transistor with an oxygen implanted emitter window | Alan S. Chen, Yih-Feng Chyan, Chung Wai Leung, William J. Nagy | 2004-11-09 |
| 6670242 | Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer | David C. Brady, Pradip K. Roy | 2003-12-30 |
| 6657281 | Bipolar transistor with a low K material in emitter base spacer regions | Yih-Feng Chyan, Chunchieh Huang, Chung Wai Leung, Shahriar Moinian | 2003-12-02 |
| 6548854 | Compound, high-K, gate and capacitor insulator layer | Isik C. Kizilyalli, Pradip K. Roy | 2003-04-15 |
| 6544907 | Method of forming a high quality gate oxide layer having a uniform thickness | Edith Yang | 2003-04-08 |
| 6537887 | Integrated circuit fabrication | Yih-Feng Chyan, Chung Wai Leung, Demi Nguyen | 2003-03-25 |
| 6518622 | Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor | Hongzong Chew, Yih-Feng Chyan, John Michael Hergenrother, Donald Monroe | 2003-02-11 |
| 6509242 | Heterojunction bipolar transistor | Michel R. Frei, Clifford A. King, Marco Mastrapasqua, Kwok Ng | 2003-01-21 |
| 6506673 | Method of forming a reverse gate structure with a spin on glass process | Huili Shao, Joseph Ashley Taylor, Allen Yen | 2003-01-14 |
| 6475842 | Process for gate oxide side-wall protection from plasma damage to form highly reliable gate dielectrics | Kean Syn Cheah, Hooi Peng Low | 2002-11-05 |
| 6451660 | Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water | Yih-Feng Chyan, Chung Wai Leung, Jane Qian Liu, Timothy Campbell | 2002-09-17 |
| 6440829 | N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure | Pradip K. Roy, Michael Laughery | 2002-08-27 |
| 6417570 | Layered dielectric film structure suitable for gate dielectric application in sub-0.25 &mgr;m technologies | Pradip K. Roy | 2002-07-09 |
| 6320238 | Gate structure for integrated circuit fabrication | Isik C. Kizilyalli, Sailesh Mansinh Merchant, Pradip K. Roy | 2001-11-20 |
| 6313007 | Semiconductor device, trench isolation structure and methods of formations | Scott F. Shive, Melissa M. Brown | 2001-11-06 |
| 6309932 | Process for forming a plasma nitride film suitable for gate dielectric application in sub-0.25 .mu.m technologies | Pradip K. Roy | 2001-10-30 |