Issued Patents All Time
Showing 76–100 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6205541 | System and method using selection logic units to define stack orders | Derrick R. Meyer | 2001-03-20 |
| 6202142 | Microcode scan unit for scanning microcode instructions using predecode data | Rammohan Narayan, Shane Southard | 2001-03-13 |
| 6192462 | Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache | David B. Witt, William M. Johnson | 2001-02-20 |
| 6167510 | Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache | — | 2000-12-26 |
| 6148393 | Apparatus for generating a valid mask | Rammohan Narayan, Shane Southard | 2000-11-14 |
| 6141748 | Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions | — | 2000-10-31 |
| 6134651 | Reorder buffer employed in a microprocessor to store instruction results having a plurality of entries predetermined to correspond to a plurality of functional units | David B. Witt | 2000-10-17 |
| 6122729 | Prefetch buffer which stores a pointer indicating an initial predecode position | — | 2000-09-19 |
| 6115792 | Way prediction logic for cache array | — | 2000-09-05 |
| 6112018 | Apparatus for exchanging two stack registers | Derrick R. Meyer | 2000-08-29 |
| 6108769 | Dependency table for reducing dependency checking hardware | Muralidharan S. Chinnakonda, Wade A. Walker | 2000-08-22 |
| 6101577 | Pipelined instruction cache and branch prediction mechanism therefor | — | 2000-08-08 |
| 6101595 | Fetching instructions from an instruction cache using sequential way prediction | James K. Pickett | 2000-08-08 |
| 6085302 | Microprocessor having address generation units for efficient generation of memory operation addresses | Rupaka Mahalingaiah | 2000-07-04 |
| 6079005 | Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address | David B. Witt | 2000-06-20 |
| 6079003 | Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache | David B. Witt | 2000-06-20 |
| 6076146 | Cache holding register for delayed update of a cache line into an instruction cache | Karthikeyan Muthusamy, Rammohan Narayan, Andrew McBride | 2000-06-13 |
| 6073230 | Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches | James K. Pickett | 2000-06-06 |
| 6065103 | Speculative store buffer | Rupaka Mahalingaiah | 2000-05-16 |
| 6065126 | Method and apparatus for executing plurality of operations per clock cycle in a single processing unit with a self-timed and self-enabled distributed clock | Rupaka Mahalingaiah | 2000-05-16 |
| 6061775 | Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types | Mauricio Calle, Shane Southard | 2000-05-09 |
| 6049863 | Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor | Rammohan Narayan, Andrew McBride, Karthikeyan Muthusamy | 2000-04-11 |
| 6032251 | Computer system including a microprocessor having a reorder buffer employing last in buffer and last in line indications | David B. Witt | 2000-02-29 |
| 6026482 | Recorder buffer and a method for allocating a fixed amount of storage for instruction results independent of a number of concurrently dispatched instructions | David B. Witt | 2000-02-15 |
| 6016533 | Way prediction logic for cache array | — | 2000-01-18 |