Issued Patents All Time
Showing 101–125 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6016545 | Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor | Rupaka Mahalingaiah, Andrew McBride | 2000-01-18 |
| 6014734 | Superscalar microprocessor configured to predict return addresses from a return stack storage | Rupaka Mahalingaiah | 2000-01-11 |
| 6012125 | Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions | — | 2000-01-04 |
| 6005793 | Multiple-bit random-access memory array | — | 1999-12-21 |
| 6006324 | High performance superscalar alignment unit | David B. Witt | 1999-12-21 |
| 6003128 | Number of pipeline stages and loop length related counter differential based end-loop prediction | — | 1999-12-14 |
| 5995749 | Branch prediction mechanism employing branch selectors to select a branch prediction | — | 1999-11-30 |
| 5991869 | Superscalar microprocessor including a high speed instruction alignment unit | David B. Witt, William M. Johnson | 1999-11-23 |
| 5987620 | Method and apparatus for a self-timed and self-enabled distributed clock | — | 1999-11-16 |
| 5987235 | Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions | — | 1999-11-16 |
| 5983342 | Superscalar microprocessor employing a future file for storing results into multiportion registers | — | 1999-11-09 |
| 5983337 | Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction | Rupaka Mahalingaiah | 1999-11-09 |
| 5983321 | Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache | Karthikeyan Muthusamy, Rammohan Narayan, Andrew McBride | 1999-11-09 |
| 5978907 | Delayed update register for an array | David B. Witt | 1999-11-02 |
| 5978906 | Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions | — | 1999-11-02 |
| 5968163 | Microcode scan unit for scanning microcode instructions using predecode data | Rammohan Narayan, Shane Southard | 1999-10-19 |
| 5961638 | Branch prediction mechanism employing branch selectors to select a branch prediction | — | 1999-10-05 |
| 5961634 | Reorder buffer having a future file for storing speculative instruction execution results | — | 1999-10-05 |
| 5960467 | Apparatus for efficiently providing memory operands for instructions | Rupaka Mahalingaiah | 1999-09-28 |
| 5954816 | Branch selector prediction | David E. Kroesche, Karthikeyan Muthusamy, Andrew McBride | 1999-09-21 |
| 5946468 | Reorder buffer having an improved future file for storing speculative instruction execution results | David B. Witt | 1999-08-31 |
| 5941981 | System for using a data history table to select among multiple data prefetch algorithms | — | 1999-08-24 |
| 5940602 | Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations | Rammohan Narayan | 1999-08-17 |
| 5933618 | Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction | James K. Pickett, Rupaka Mahalingaiah | 1999-08-03 |
| 5930489 | Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets | John G. Bartkowiak | 1999-07-27 |