Issued Patents All Time
Showing 151–175 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5848287 | Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches | David B. Witt, William M. Johnson | 1998-12-08 |
| 5845101 | Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache | William M. Johnson, Matt T. Gavin, Mike Pedneau | 1998-12-01 |
| 5835968 | Apparatus for providing memory and register operands concurrently to functional units | Rupaka Mahalingaiah | 1998-11-10 |
| 5835744 | Microprocessor configured to swap operands in order to minimize dependency checking logic | David B. Witt, William M. Johnson | 1998-11-10 |
| 5832297 | Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations | H. S. Ramagopal, James K. Pickett | 1998-11-03 |
| 5832249 | High performance superscalar alignment unit | David B. Witt | 1998-11-03 |
| 5822575 | Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction | — | 1998-10-13 |
| 5822558 | Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor | — | 1998-10-13 |
| 5822559 | Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions | Rammohan Narayan | 1998-10-13 |
| 5822574 | Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same | — | 1998-10-13 |
| 5819057 | Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units | David B. Witt | 1998-10-06 |
| 5819059 | Predecode unit adapted for variable byte-length instruction set processors and method of operating the same | — | 1998-10-06 |
| 5813045 | Conditional early data address generation mechanism for a microprocessor | Rupaka Mahalingaiah, David B. Witt | 1998-09-22 |
| 5794028 | Shared branch prediction structure | — | 1998-08-11 |
| 5787266 | Apparatus and method for accessing special registers without serialization | William M. Johnson, Rupaka Mahalingaiah | 1998-07-28 |
| 5768553 | Microprocessor using an instruction field to define DSP instructions | — | 1998-06-16 |
| 5768555 | Reorder buffer employing last in buffer and last in line bits | David B. Witt | 1998-06-16 |
| 5764946 | Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address | James K. Pickett | 1998-06-09 |
| 5765035 | Recorder buffer capable of detecting dependencies between accesses to a pair of caches | — | 1998-06-09 |
| 5761712 | Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array | James K. Pickett | 1998-06-02 |
| 5761137 | DRAM access system and method | William M. Johnson, Stephen C. Kromer | 1998-06-02 |
| 5758114 | High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor | William M. Johnson, David B. Witt | 1998-05-26 |
| 5752259 | Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache | — | 1998-05-12 |
| 5748978 | Byte queue divided into multiple subqueues for optimizing instruction selection logic | Rammohan Narayan | 1998-05-05 |
| 5713039 | Register file having multiple register storages for storing data from multiple data streams | — | 1998-01-27 |