Issued Patents All Time
Showing 126–150 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5920710 | Apparatus and method for modifying status bits in a reorder buffer with a large speculative state | Teik-Chung Tan | 1999-07-06 |
| 5919251 | Search mechanism for a rotating pointer buffer | — | 1999-07-06 |
| 5915110 | Branch misprediction recovery in a reorder buffer having a future file | David B. Witt | 1999-06-22 |
| 5909587 | Multi-chip superscalar microprocessor module | — | 1999-06-01 |
| 5903910 | Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline | Marty Pflum, David B. Witt, William M. Johnson | 1999-05-11 |
| 5903741 | Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions | David B. Witt | 1999-05-11 |
| 5901302 | Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions | David B. Witt | 1999-05-04 |
| 5900012 | Storage device having varying access times and a superscalar microprocessor employing the same | — | 1999-05-04 |
| 5898851 | Method and apparatus for five bit predecoding variable length instructions for scanning of a number of RISC operations | Rammohan Narayan | 1999-04-27 |
| 5898849 | Microprocessor employing local caches for functional units to store memory operands used by the functional units | — | 1999-04-27 |
| 5892936 | Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register | James K. Pickett, Rupaka Mahalingaiah | 1999-04-06 |
| 5890006 | Apparatus for extracting instruction specific bytes from an instruction | Mauricio Calle, Shane Southard | 1999-03-30 |
| 5887152 | Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions | — | 1999-03-23 |
| 5881278 | Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch | Rupaka Mahalingaiah | 1999-03-09 |
| 5878255 | Update unit for providing a delayed update to a branch prediction array | David B. Witt | 1999-03-02 |
| 5878244 | Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received | David B. Witt | 1999-03-02 |
| 5875324 | Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock | David B. Witt | 1999-02-23 |
| 5872951 | Reorder buffer having a future file for storing speculative instruction execution results | — | 1999-02-16 |
| 5872943 | Apparatus for aligning instructions using predecoded shift amounts | James K. Pickett | 1999-02-16 |
| 5864689 | Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction | — | 1999-01-26 |
| 5864707 | Superscalar microprocessor configured to predict return addresses from a return stack storage | Rupaka Mahalingaiah | 1999-01-26 |
| 5859992 | Instruction alignment using a dispatch list and a latch list | Rammohan Narayan, Jagadish V. Nayak | 1999-01-12 |
| 5852727 | Instruction scanning unit for locating instructions via parallel scanning of start and end byte information | Rammohan Narayan | 1998-12-22 |
| 5850532 | Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched | Rammohan Narayan, Shane Southard | 1998-12-15 |
| 5848433 | Way prediction unit and a method for operating the same | James K. Pickett | 1998-12-08 |