Issued Patents All Time
Showing 51–75 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8065506 | Application specific instruction set processor for digital radio processor receiving chain signal processing | Jinwen Xi, Roman Staszewski | 2011-11-22 |
| 7890735 | Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture | — | 2011-02-15 |
| D629310 | Modular pulp package | — | 2010-12-21 |
| 7752426 | Processes, circuits, devices, and systems for branch prediction and other processor improvements | Jeffrey L. Nye | 2010-07-06 |
| 7475231 | Loop detection and capture in the instruction queue | — | 2009-01-06 |
| 7330936 | System and method for power efficient memory caching | Muralidharan S. Chinnakonda, Rajinder Singh | 2008-02-12 |
| 7330964 | Microprocessor with independent SIMD loop buffer | Muralidharan S. Chinnakonda | 2008-02-12 |
| 7328332 | Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages | — | 2008-02-05 |
| 7266676 | Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays | Ravi P. Singh, Deepa Duraiswamy, Srikanth Kannan | 2007-09-04 |
| 7237065 | Configurable cache system depending on instruction type | Raul A. Garibay, Jr., Muralidharan S. Chinnakonda, Paul K. Miller | 2007-06-26 |
| 7134000 | Methods and apparatus for instruction alignment including current instruction pointer logic responsive to instruction length information | Ravi P. Singh, Deepa Duraiswamy, Srikanth Kannan | 2006-11-07 |
| 6963962 | Memory system for supporting multiple parallel accesses at very high frequencies | Hebbalalu S. Ramagopal, Murali Chinnakonda | 2005-11-08 |
| 6604190 | Data address prediction structure and a method for operating the same | — | 2003-08-05 |
| 6393549 | Instruction alignment unit for routing variable byte-length instructions | David B. Witt | 2002-05-21 |
| 6381689 | Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction | David B. Witt | 2002-04-30 |
| 6367006 | Predecode buffer including buffer pointer indicating another buffer for predecoding | — | 2002-04-02 |
| 6292884 | Reorder buffer employing last in line indication | David B. Witt | 2001-09-18 |
| 6279107 | Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions | — | 2001-08-21 |
| 6269436 | Superscalar microprocessor configured to predict return addresses from a return stack storage | Rupaka Mahalingaiah | 2001-07-31 |
| 6266752 | Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache | David B. Witt | 2001-07-24 |
| 6253316 | Three state branch history using one bit in a branch prediction mechanism | Andrew McBride, Karthikeyan Muthusamy | 2001-06-26 |
| 6249862 | Dependency table for reducing dependency checking hardware | Muralidharan S. Chinnakonda, Wade A. Walker | 2001-06-19 |
| 6247123 | Branch prediction mechanism employing branch selectors to select a branch prediction | — | 2001-06-12 |
| 6237082 | Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received | David B. Witt | 2001-05-22 |
| 6209084 | Dependency table for reducing dependency checking hardware | Muralidharan S. Chinnakonda, Wade A. Walker | 2001-03-27 |