Issued Patents All Time
Showing 26–50 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10552158 | Reorder buffer scoreboard having multiple valid bits to indicate a location of data | — | 2020-02-04 |
| 10318302 | Thread switching in microprocessor without full save and restore of register file | — | 2019-06-11 |
| 9672044 | Space efficient checkpoint facility and technique for processor with integrally indexed register mapping and free-list arrays | — | 2017-06-06 |
| 9658857 | Method and apparatus for processor to operate at its natural clock frequency in the system | — | 2017-05-23 |
| 9547593 | Systems and methods for reconfiguring cache memory | — | 2017-01-17 |
| 9524162 | Apparatus and method for memory copy at a processor | James H. C. Yang | 2016-12-20 |
| 9424190 | Data processing system operable in single and multi-thread modes and having multiple caches and method of operation | — | 2016-08-23 |
| 9417920 | Method and apparatus for dynamic resource partition in simultaneous multi-thread microprocessor | — | 2016-08-16 |
| 9389869 | Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines | — | 2016-07-12 |
| 9170818 | Register renaming scheme with checkpoint repair in a processing device | — | 2015-10-27 |
| 9141391 | Data processing system with latency tolerance execution | Trinh Huy Nguyen | 2015-09-22 |
| 9135014 | Data processing system with latency tolerance execution | Trinh Huy Nguyen | 2015-09-15 |
| 9110656 | Systems and methods for handling instructions of in-order and out-of-order execution queues | Trinh Huy Nguyen | 2015-08-18 |
| 9092225 | Systems and methods for reducing branch misprediction penalty | Michael Brian SCHINZLER | 2015-07-28 |
| 9063747 | Microprocessor systems and methods for a combined register file and checkpoint repair register | — | 2015-06-23 |
| 9015504 | Managing power of thread pipelines according to clock frequency and voltage specified in thread registers | — | 2015-04-21 |
| 8984254 | Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance | Edmund J. Gieske | 2015-03-17 |
| 8972700 | Microprocessor systems and methods for latency tolerance execution | — | 2015-03-03 |
| 8966229 | Systems and methods for handling instructions of in-order and out-of-order execution queues | Trinh Huy Nguyen | 2015-02-24 |
| 8966232 | Data processing system operable in single and multi-thread modes and having multiple caches and method of operation | — | 2015-02-24 |
| 8959371 | Techniques for reducing processor power consumption through dynamic processor resource allocation | — | 2015-02-17 |
| 8904150 | Microprocessor systems and methods for handling instructions with multiple dependencies | Leick D. Robinson | 2014-12-02 |
| 8639884 | Systems and methods for configuring load/store execution units | — | 2014-01-28 |
| 8458447 | Branch target buffer addressing in a data processor | Edmund J. Gieske, Michael Brian SCHINZLER | 2013-06-04 |
| D656037 | Tubular pouch package | — | 2012-03-20 |