Issued Patents All Time
Showing 201–225 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5847579 | Programmable logic array with improved interconnect structure | — | 1998-12-08 |
| 5847577 | DRAM memory cell for programmable logic devices | — | 1998-12-08 |
| 5844844 | FPGA memory element programmably triggered on both clock edges | Trevor J. Bauer, Steven P. Young | 1998-12-01 |
| 5844829 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, John E. Mahoney, Charles R. Erickson | 1998-12-01 |
| 5844422 | State saving and restoration in reprogrammable FPGAs | Jonathan Rose | 1998-12-01 |
| 5838954 | Computer-implemented method of optimizing a time multiplexed programmable logic device | — | 1998-11-17 |
| 5831907 | Repairable memory cell for a memory cell array | — | 1998-11-03 |
| 5825202 | Integrated circuit with field programmable and application specific logic areas | Danesh Tavana, Wilson K. Yee | 1998-10-20 |
| 5825662 | Computer-implemented method of optimizing a time multiplexed programmable logic device | — | 1998-10-20 |
| 5815004 | Multi-buffered configurable logic block output lines in a field programmable gate array | Khue Duong | 1998-09-29 |
| 5811985 | Output multiplexer circuit for input/output block | Khue Duong, Robert O. Conn | 1998-09-22 |
| 5784313 | Programmable logic device including configuration data or user data memory slices | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1998-07-21 |
| 5778439 | Programmable logic device with hierarchical confiquration and state storage | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1998-07-07 |
| 5773993 | Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable electronic device | — | 1998-06-30 |
| 5761483 | Optimizing and operating a time multiplexed programmable logic device | — | 1998-06-02 |
| 5752035 | Method for compiling and executing programs for reprogrammable instruction set accelerator | — | 1998-05-12 |
| 5748979 | Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table | — | 1998-05-05 |
| 5742531 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, John E. Mahoney, Charles R. Erickson | 1998-04-21 |
| 5737631 | Reprogrammable instruction set accelerator | — | 1998-04-07 |
| 5712579 | Deskewed clock distribution network with edge clock | Khue Duong, Robert O. Conn, John E. Mahoney | 1998-01-27 |
| 5703759 | Multi-chip electrically reconfigurable module with predominantly extra-package inter-chip connections | — | 1997-12-30 |
| 5701441 | Computer-implemented method of optimizing a design in a time multiplexed programmable logic device | — | 1997-12-23 |
| 5696454 | Hierarchical programming of electrically configurable integrated circuits | — | 1997-12-09 |
| 5694056 | Fast pipeline frame full detector | John E. Mahoney, Charles R. Erickson | 1997-12-02 |
| 5675262 | Fast carry-out scheme in a field programmable gate array | Khue Duong, Bernard J. New | 1997-10-07 |