Issued Patents All Time
Showing 176–200 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6255675 | Programmable capacitor for an integrated circuit | — | 2001-07-03 |
| 6242947 | PLD having a window pane architecture with segmented interconnect wiring between logic block arrays | — | 2001-06-05 |
| 6173241 | Logic simulator which can maintain, store, and use historical event records | — | 2001-01-09 |
| 6167558 | Method for tolerating defective logic blocks in programmable logic devices | — | 2000-12-26 |
| 6105105 | Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution | — | 2000-08-15 |
| 6094065 | Integrated circuit with field programmable and application specific logic areas | Danesh Tavana, Wilson K. Yee | 2000-07-25 |
| 6094385 | Repairable memory cell for a memory cell array | — | 2000-07-25 |
| 6084429 | PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays | — | 2000-07-04 |
| 6047115 | Method for configuring FPGA memory planes for virtual hardware computation | Sundararajarao Mohan | 2000-04-04 |
| 6037800 | Method for programming a programmable gate array having shared signal lines for interconnect and configuration | — | 2000-03-14 |
| 6023564 | Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions | — | 2000-02-08 |
| 6016063 | Method and apparatus for connecting long lines to form wide logic functions | — | 2000-01-18 |
| 6011740 | Structure and method for providing additional configuration memories on an FPGA | — | 2000-01-04 |
| 5995419 | Repairable memory cell for a memory cell array | — | 1999-11-30 |
| 5995988 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, John E. Mahoney, Charles R. Erickson | 1999-11-30 |
| 5986467 | Time-multiplexed programmable logic devices | — | 1999-11-16 |
| 5978260 | Method of time multiplexing a programmable logic device | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1999-11-02 |
| 5973506 | Method and apparatus for connecting long lines to form wide busses | — | 1999-10-26 |
| 5961576 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, John E. Mahoney, Charles R. Erickson | 1999-10-05 |
| 5959881 | Programmable logic device including configuration data or user data memory slices | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1999-09-28 |
| 5944813 | FPGA input output buffer with registered tristate enable | — | 1999-08-31 |
| 5910732 | Programmable gate array having shared signal lines for interconnect and configuration | — | 1999-06-08 |
| 5896329 | Repairable memory cell for a memory cell array | — | 1999-04-20 |
| 5892961 | Field programmable gate array having programming instructions in the configuration bitstream | — | 1999-04-06 |
| 5880492 | Dedicated local line interconnect layout | Khue Duong | 1999-03-09 |