Issued Patents All Time
Showing 226–250 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5656950 | Interconnect lines including tri-directional buffer circuits | Khue Duong | 1997-08-12 |
| 5652904 | Non-reconfigurable microprocessor-emulated FPGA | — | 1997-07-29 |
| 5650946 | Logic simulator which can maintain, store and use historical event records | — | 1997-07-22 |
| 5646545 | Time multiplexed programmable logic device | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1997-07-08 |
| 5642058 | Periphery input/output interconnect structure | Khue Duong | 1997-06-24 |
| 5629637 | Method of time multiplexing a programmable logic device | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1997-05-13 |
| 5610829 | Method for programming an FPLD using a library-based technology mapping algorithm | — | 1997-03-11 |
| 5608342 | Hierarchical programming of electrically configurable integrated circuits | — | 1997-03-04 |
| 5600263 | Configuration modes for a time multiplexed programmable logic device | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1997-02-04 |
| 5600264 | Programmable single buffered six pass transistor configuration | Khue Duong, Alok Mehrotra | 1997-02-04 |
| 5594367 | Output multiplexer within input/output circuit for time multiplexing and high speed logic | Khue Duong, Robert O. Conn | 1997-01-14 |
| 5583450 | Sequencer for a time multiplexed programmable logic device | Richard A. Carberry, Robert Anders Johnson, Jennifer Wong | 1996-12-10 |
| 5583452 | Tri-directional buffer | Khue Duong | 1996-12-10 |
| 5581198 | Shadow DRAM for programmable logic devices | — | 1996-12-03 |
| 5521835 | Method for programming an FPLD using a library-based technology mapping algorithm | — | 1996-05-28 |
| 5513124 | Logic placement using positionally asymmetrical partitioning method | Mon-Ren Chene | 1996-04-30 |
| 5500608 | Logic cell for field programmable gate array having optional internal feedback and optional cascade | F. Erich Goetting | 1996-03-19 |
| 5498979 | Adaptive programming method for antifuse technology | David B. Parlour, F. Erich Goetting, Edel M. Young | 1996-03-12 |
| 5448493 | Structure and method for manually controlling automatic configuration in an integrated circuit logic block array | Todd J. Topolewski, Christine M. Weir, Bart Reynolds, Julia M. Smuts, Pardner Wynn | 1995-09-05 |
| 5426379 | Field programmable gate array with built-in bitstream data expansion | — | 1995-06-20 |
| 5386154 | Compact logic cell for field programmable gate array chip | F. Erich Goetting, David B. Parlour | 1995-01-31 |
| 5365125 | Logic cell for field programmable gate array having optional internal feedback and optional cascade | F. Erich Goetting | 1994-11-15 |
| 5349248 | Adaptive programming method for antifuse technology | David B. Parlour, F. Erich Goetting | 1994-09-20 |
| 5224056 | Logic placement using positionally asymmetrical partitioning algorithm | Mon-Ren Chene | 1993-06-29 |
| 4745084 | Method of making a customized semiconductor integrated device | James A. Rowson | 1988-05-17 |