Issued Patents All Time
Showing 51–62 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| D562890 | Pen | Kung Hua Lin | 2008-02-26 |
| 7335594 | Method for manufacturing a memory device having a nanocrystal charge storage region | Zoran Krivokapic, Suzette K. Pangrle, Jinsong Yin | 2008-02-26 |
| 7309650 | Memory device having a nanocrystal charge storage region and method | Lu You, Zoran Krivokapic, Paul R. Besser, Suzette K. Pangrle | 2007-12-18 |
| 7217660 | Method for manufacturing a semiconductor component that inhibits formation of wormholes | Paul R. Besser, Jinsong Yin, Hieu Pham, Minh Van Ngo | 2007-05-15 |
| 7033940 | Method of forming composite barrier layers with controlled copper interface surface roughness | Amit P. Marathe, Christy Mei-Chu Woo, Paul L. King | 2006-04-25 |
| 6979642 | Method of self-annealing conductive lines that separates grain size effects from alloy mobility | Matthew S. Buynoski, Paul R. Besser, Minh Quoc Tran | 2005-12-27 |
| 6979625 | Copper interconnects with metal capping layer and selective copper alloys | Christy Mei-Chu Woo, Darrell M. Erb | 2005-12-27 |
| 6952052 | Cu interconnects with composite barrier layers for wafer-to-wafer uniformity | Amit P. Marathe, Christy Mei-Chu Woo | 2005-10-04 |
| 6943096 | Semiconductor component and method of manufacture | Suzette K. Pangrle, Sergey Lopatin | 2005-09-13 |
| 6927162 | Method of forming a contact in a semiconductor device with formation of silicide prior to plasma treatment | Wen Yu, Jinsong Yin, Paul R. Besser, Keizaburo Yoshie | 2005-08-09 |
| 6509267 | Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer | Christy Mei-Chu Woo, Suzette K. Pangrle | 2003-01-21 |
| 6506668 | Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability | Christy Mei-Chu Woo, Steve Avanzino | 2003-01-14 |