Issued Patents 2025
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12310044 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim +1 more | 2025-05-20 |
| 12302632 | Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process | Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu +2 more | 2025-05-13 |
| 12295170 | Fabrication of gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer | Dan S. LAVRIC, Dax M. Crum, Omair Saadat, Oleg Golonzka | 2025-05-06 |
| 12294006 | Gate-all-around integrated circuit structures having insulator substrate | Chung-Hsun Lin, Biswajeet Guha, William Hsu, Stephen M. Cea | 2025-05-06 |
| 12294027 | Semiconductor device having doped epitaxial region and its methods of fabrication | Anand S. Murthy, Daniel B. Aubertine, Abhijit Jayant Pethe | 2025-05-06 |
| 12288807 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Aaron D. Lilak, Rishabh Mehandru, Willy Rachmady, Harold W. Kennel | 2025-04-29 |
| 12288789 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more | 2025-04-29 |
| 12288803 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more | 2025-04-29 |
| 12278144 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani | 2025-04-15 |
| 12272737 | Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact | Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka | 2025-04-08 |
| 12266571 | Self-aligned contacts | Mark Bohr, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2025-04-01 |
| 12266708 | Integrated circuit structures having dielectric anchor void | Leonard P. GULER, Charles H. Wallace | 2025-04-01 |
| 12255234 | Integrated circuit structures having germanium-based channels | Siddharth Chouksey, Glenn A. Glass, Anand S. Murthy, Harold W. Kennel, Jack T. Kavalieros +2 more | 2025-03-18 |
| 12243875 | Forksheet transistors with dielectric or conductive spine | Seung Hoon Sung, Cheng-Ying Huang, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose +4 more | 2025-03-04 |
| 12237420 | Fin smoothing and integrated circuit structures resulting therefrom | Cory Bomberger, Anand S. Murthy, Anupama Bowonder | 2025-02-25 |
| 12238913 | Two transistor memory cell using stacked thin-film transistors | Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-Hua Wang +5 more | 2025-02-25 |
| 12230717 | Integrated circuit structures having partitioned source or drain contact structures | Mauro J. Kobrinsky, Stephanie A. Bojarski, Babita Dhayal, Biswajeet Guha | 2025-02-18 |
| 12230721 | Gate-all-around integrated circuit structures having asymmetric source and drain contact structures | Biswajeet Guha, Mauro J. Kobrinsky | 2025-02-18 |
| 12224350 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Biswajeet Guha, William Hsu, Leonard P. GULER, Dax M. Crum | 2025-02-11 |
| 12211925 | Gate-all-around integrated circuit structures having oxide sub-fins | Leonard P. GULER, Biswajeet Guha, Swaminathan Sivakumar | 2025-01-28 |
| 12205955 | Fins for metal oxide semiconductor device structures | Martin D. Giles | 2025-01-21 |
| 12206027 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Susmita Ghose, Zachary Geiger | 2025-01-21 |
| 12199143 | Gate-all-around integrated circuit structures having removed substrate | Biswajeet Guha, Mauro J. Kobrinsky, Patrick Morrow, Oleg Golonzka | 2025-01-14 |
| 12191308 | Non-planar semiconductor device having doped sub-fin region and method to fabricate same | Salman Latif, Chanaka D. Munasinghe | 2025-01-07 |
| 12191349 | Reducing off-state leakage in semiconductor devices | Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel +3 more | 2025-01-07 |