Issued Patents 2025
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414366 | Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation | Prashant Majhi, Anand S. Murthy, Glenn A. Glass, Rushabh SHAH | 2025-09-09 |
| 12272727 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Cory Bomberger, Anand S. Murthy, Siddharth Chouksey | 2025-04-08 |
| 12243875 | Forksheet transistors with dielectric or conductive spine | Seung Hoon Sung, Cheng-Ying Huang, Marko Radosavljevic, Christopher M. Neumann, Varun MISHRA +4 more | 2025-03-04 |
| 12206027 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Tahir Ghani, Zachary Geiger | 2025-01-21 |