Issued Patents 2025
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414339 | Formation of gate spacers for strained PMOS gate-all-around transistor structures | Ashish Agrawal, Gilbert Dewey, Jack T. Kavalieros, Cheng-Ying Huang | 2025-09-09 |
| 12328927 | Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures | Gilbert Dewey, Nazila Haratipour, Arnab Sen Gupta, Christopher J. Jezewski, I-Cheng Tung +2 more | 2025-06-10 |
| 12272727 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Cory Bomberger, Anand S. Murthy, Susmita Ghose | 2025-04-08 |
| 12266570 | Self-aligned interconnect structures and methods of fabrication | Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Jessica M. Torres +5 more | 2025-04-01 |
| 12255234 | Integrated circuit structures having germanium-based channels | Glenn A. Glass, Anand S. Murthy, Harold W. Kennel, Jack T. Kavalieros, Tahir Ghani +2 more | 2025-03-18 |
| 12199142 | Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions | Jack T. Kavalieros, Stephen M. Cea, Ashish Agrawal, Willy Rachmady | 2025-01-14 |