Issued Patents 2025
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433007 | Transistor gate trench engineering to decrease capacitance and resistance | Seung Hoon Sung, Jack T. Kavalieros, Han Wui Then, Marko Radosavljevic | 2025-09-30 |
| 12388011 | Top gate recessed channel CMOS thin film transistor and methods of fabrication | Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal +1 more | 2025-08-12 |
| 12369399 | Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure | Sudipto Naskar, Cheng-Ying Huang, Gilbert Dewey, Marko Radosavljevic, Nicole K. Thomas +2 more | 2025-07-22 |
| 12363967 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more | 2025-07-15 |
| 12342614 | Asymmetric gate structures and contacts for stacked transistors | Cheng-Ying Huang, Patrick Morrow, Arunshankar Venkataraman, Sean T. Ma, Nicole K. Thomas +2 more | 2025-06-24 |
| 12288813 | Gate-all-around integrated circuit structures having insulator fin on insulator substrate | Aaron D. Lilak, Rishabh Mehandru, Cory E. Weber, Varun MISHRA | 2025-04-29 |
| 12288803 | Transistor with isolation below source and drain | Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy +3 more | 2025-04-29 |
| 12288807 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Aaron D. Lilak, Rishabh Mehandru, Harold W. Kennel, Tahir Ghani | 2025-04-29 |
| 12266570 | Self-aligned interconnect structures and methods of fabrication | Kimin Jun, Souvik Ghosh, Ashish Agrawal, Siddharth Chouksey, Jessica M. Torres +5 more | 2025-04-01 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2025-03-18 |
| 12224202 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more | 2025-02-11 |
| 12199142 | Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions | Siddharth Chouksey, Jack T. Kavalieros, Stephen M. Cea, Ashish Agrawal | 2025-01-14 |