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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Patrick Morrow — 9 Patents in 2025

Intel: 9 patents #167 of 3,896Top 5%
Portland, OR: #120 of 1,645 inventorsTop 8%
Oregon: #178 of 3,620 inventorsTop 5%
Overall (2025): #9,144 of 469,880Top 2%
9 Patents 2025

Issued Patents 2025

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
12506059 Vertically spaced intra-level interconnect line metallization for integrated circuit devices Keh-I Lin, Sukru YEMENICIOGLU, Richard E. Schenker, Mauro J. Kobrinsky 2025-12-23
12446204 SRAM with P-type access transistors and complementary field-effect transistor technology Charles Augustine, Seenivasan Subramaniam, Muhammad M. Khellah 2025-10-14
12369399 Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Gilbert Dewey, Marko Radosavljevic +2 more 2025-07-22
12342614 Asymmetric gate structures and contacts for stacked transistors Cheng-Ying Huang, Arunshankar Venkataraman, Sean T. Ma, Willy Rachmady, Nicole K. Thomas +2 more 2025-06-24
12310044 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Rishabh Mehandru, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more 2025-05-20
12288810 Backside contact structures and fabrication for metal on both sides of devices Rishabh Mehandru, Aaron D. Lilak, Kimin Jun 2025-04-29
12255137 Sideways vias in isolation areas to contact interior layers in stacked devices Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Anh Phan, Willy Rachmady +3 more 2025-03-18
12224202 Forming an oxide volume within a fin Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more 2025-02-11
12199143 Gate-all-around integrated circuit structures having removed substrate Biswajeet Guha, Mauro J. Kobrinsky, Oleg Golonzka, Tahir Ghani 2025-01-14