{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "2025", "item": "https://www.patentleaderboard.com/2025/"}, {"@type": "ListItem", "position": 3, "name": "Intel", "item": "https://www.patentleaderboard.com/2025/company/intel"}, {"@type": "ListItem", "position": 4, "name": "Gilbert Dewey", "item": "https://www.patentleaderboard.com/2025/inventor/fl:gi_ln:dewey-2"}]}

Home › 2025 › Intel › Gilbert Dewey

GD

Gilbert Dewey — 14 Patents in 2025

Intel: 14 patents #65 of 3,896Top 2%

Beaverton, OR: #11 of 434 inventorsTop 3%

Oregon: #66 of 3,620 inventorsTop 2%

Overall (2025): #3,868 of 469,880Top 1%

14 Patents 2025

Issued Patents 2025

Showing 1–14 of 14 patents

Patent #	Title	Co-Inventors	Date
12457778	Conductive contacts wrapped around epitaxial source or drain regions	Leonard P. GULER, Saurabh Morarka, Sikandar Abbas, Moh'd A. Hasan	2025-10-28
12439669	Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts	Debaleena Nandi, Chi Choi, Harold W. Kennel, Omair Saadat, Jitendra Kumar Jha +4 more	2025-10-07
12426342	Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability	Debaleena Nandi, Cory Bomberger, Anand S. Murthy, Mauro J. Kobrinsky, Rushabh SHAH +6 more	2025-09-23
12414339	Formation of gate spacers for strained PMOS gate-all-around transistor structures	Ashish Agrawal, Siddharth Chouksey, Jack T. Kavalieros, Cheng-Ying Huang	2025-09-09
12388011	Top gate recessed channel CMOS thin film transistor and methods of fabrication	Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more	2025-08-12
12376362	Field effect transistors with a gated oxide semiconductor source/drain spacer	Rafael Rios, Van H. Le, Jack T. Kavalieros	2025-07-29
12369399	Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure	Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Marko Radosavljevic, Nicole K. Thomas +2 more	2025-07-22
12349416	Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures	Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Seung Hoon Sung +4 more	2025-07-01
12342574	Contact resistance reduction in transistor devices with metallization on both sides	Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Glenn A. Glass, Anand S. Murthy +2 more	2025-06-24
12328927	Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures	Nazila Haratipour, Siddharth Chouksey, Arnab Sen Gupta, Christopher J. Jezewski, I-Cheng Tung +2 more	2025-06-10
12288803	Transistor with isolation below source and drain	Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more	2025-04-29
12255137	Sideways vias in isolation areas to contact interior layers in stacked devices	Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more	2025-03-18
12224202	Forming an oxide volume within a fin	Cheng-Ying Huang, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more	2025-02-11
12191395	Dual gate control for trench shaped thin film transistors	Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung +2 more	2025-01-07