Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
Partial year: Data through Q3 2025 (Sept 30). Full-year totals not yet available.
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Gilbert Dewey — 12 Patents in 2025

Intel: 12 patents #60 of 3,896Top 2%
Beaverton, OR: #14 of 434 inventorsTop 4%
Oregon: #71 of 3,620 inventorsTop 2%
Overall (2025): #4,357 of 469,880Top 1%
12 Patents 2025

Issued Patents 2025

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
12426342 Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability Debaleena Nandi, Cory Bomberger, Anand S. Murthy, Mauro J. Kobrinsky, Rushabh SHAH +6 more 2025-09-23
12414339 Formation of gate spacers for strained PMOS gate-all-around transistor structures Ashish Agrawal, Siddharth Chouksey, Jack T. Kavalieros, Cheng-Ying Huang 2025-09-09
12388011 Top gate recessed channel CMOS thin film transistor and methods of fabrication Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more 2025-08-12
12376362 Field effect transistors with a gated oxide semiconductor source/drain spacer Rafael Rios, Van H. Le, Jack T. Kavalieros 2025-07-29
12369399 Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Marko Radosavljevic, Nicole K. Thomas +2 more 2025-07-22
12349416 Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Seung Hoon Sung +4 more 2025-07-01
12342574 Contact resistance reduction in transistor devices with metallization on both sides Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Glenn A. Glass, Anand S. Murthy +2 more 2025-06-24
12328927 Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures Nazila Haratipour, Siddharth Chouksey, Arnab Sen Gupta, Christopher J. Jezewski, I-Cheng Tung +2 more 2025-06-10
12288803 Transistor with isolation below source and drain Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more 2025-04-29
12255137 Sideways vias in isolation areas to contact interior layers in stacked devices Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more 2025-03-18
12224202 Forming an oxide volume within a fin Cheng-Ying Huang, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more 2025-02-11
12191395 Dual gate control for trench shaped thin film transistors Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung +2 more 2025-01-07