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USPTO Patent Rankings Data through Dec 31, 2025
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Gerald Pasdast — 19 Patents in 2025

Intel: 19 patents #36 of 3,896Top 1%
San Jose, CA: #45 of 5,639 inventorsTop 1%
California: #401 of 55,090 inventorsTop 1%
Overall (2025): #2,170 of 469,880Top 1%
19 Patents 2025

Issued Patents 2025

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDate
12505065 On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY Debendra Das Sharma, Narasimha Lanka, Peter Z. Onufryk, Swadesh Choudhary, Zuoguo Wu +2 more 2025-12-23
12499019 Retimers to extend a die-to-die interconnect Debendra Das Sharma, Swadesh Choudhary, Sridhar Muthrasanallur, Narasimha Lanka, Zuoguo Wu +1 more 2025-12-16
12499074 Die-to-die interconnect protocol layer Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Lakshmi Narasimhan Seshan, Zuoguo Wu 2025-12-16
12500583 Clock interpolation system for eye-centering Jayen Desai, Pengyin WANG, Debendra Das Sharma 2025-12-16
12481614 Standard interfaces for die to die (D2D) interconnect stacks Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Zuoguo Wu, Lakshmi Narasimhan Seshan 2025-11-25
12469820 Fine-grained disaggregated server architecture Carleton L. Molnar, Adel A. Elsherbini, Tanay Karnik, Shawna M. Liff, Robert J. Munoz +6 more 2025-11-11
12468597 Valid signal for latency sensitive die-to-die (D2D) interconnects Narasimha Lanka, Debendra Das Sharma, Lakshmi Narasimhan Seshan, Swadesh Choudhary, Zuoguo Wu 2025-11-11
12405912 Link initialization training and bring up for die-to-die interconnect Narasimha Lanka, Lakshmipriya Seshan, Swadesh Choudhary, Debendra Das Sharma, Zuoguo Wu 2025-09-02
12406962 Power delivery through capacitor-dies in a multi-layered microelectronic assembly Adel A. Elsherbini, William J. Lambert, Krishna Bharath, Shawna M. Liff, Nicolas Butzen +4 more 2025-09-02
12362306 Clock-gating in die-to-die (D2D) interconnects Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Swadesh Choudhary 2025-07-15
12362284 Composite interposer structure and method of providing same Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan 2025-07-15
12353305 Compliance and debug testing of a die-to-die interconnect Swadesh Choudhary, Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu 2025-07-08
12332826 Die-to-die interconnect Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan, Zuoguo Wu 2025-06-17
12321305 Sideband interface for die-to-die interconnects Narasimha Lanka, Swadesh Choudhary, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu 2025-06-03
12316343 PHY-based retry techniques for die-to-die interfaces Narasimha Lanka, Lakshmipriya Seshan, Debendra Das Sharma, Zuoguo Wu 2025-05-27
12315794 Skip level vias in metallization layers for integrated circuit devices Adel A. Elsherbini, Mauro J. Kobrinsky, Shawna M. Liff, Johanna M. Swan, Sathya Narasimman Tiagaraj 2025-05-27
12306216 Dynamic voltage regulator sensing for chiplet-based designs Vikrant Thigle, Vijay Anand Mathiyalagan, Anand Haridass, Arun Chandrasekhar 2025-05-20
12288746 Skip level vias in metallization layers for integrated circuit devices Adel A. Elsherbini, Mauro J. Kobrinsky, Shawna M. Liff, Johanna M. Swan, Sathya Narasimman Tiagaraj 2025-04-29
12266682 Capacitors and resistors at direct bonding interfaces in microelectronic assemblies Adel A. Elsherbini, Mohammad Enamul Kabir, Zhiguo Qian, Kimin Jun, Shawna M. Liff +3 more 2025-04-01