Issued Patents 2025
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405912 | Link initialization training and bring up for die-to-die interconnect | Narasimha Lanka, Lakshmipriya Seshan, Debendra Das Sharma, Zuoguo Wu, Gerald Pasdast | 2025-09-02 |
| 12373279 | Selection of processing mode for receiver circuit | Debendra Das Sharma, Michelle C. Jen | 2025-07-29 |
| 12360934 | Parameter exchange for a die-to-die interconnect | Debendra Das Sharma, Mahesh S. Natu, Sridhar Muthrasanallur, Narasimha Lanka, Lakshmipriya Seshan | 2025-07-15 |
| 12362306 | Clock-gating in die-to-die (D2D) interconnects | Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu | 2025-07-15 |
| 12353305 | Compliance and debug testing of a die-to-die interconnect | Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast | 2025-07-08 |
| 12332826 | Die-to-die interconnect | Debendra Das Sharma, Narasimha Lanka, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu | 2025-06-17 |
| 12332752 | Hardware logging for lane margining and characterization | Debendra Das Sharma, Michelle C. Jen, Raghucharan Boddupalli | 2025-06-17 |
| 12321305 | Sideband interface for die-to-die interconnects | Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast | 2025-06-03 |
| 12298833 | Performance level control in a data processing apparatus | Ujjwal Gupta, Ankush Varma, Lakshmipriya Seshan, Nikethan Shivanand Baligar, Nikhil Gupta +1 more | 2025-05-13 |
| 12244326 | Encoder and decoder of forward error correction (FEC) codec | Debendra Das Sharma | 2025-03-04 |
| 12222881 | Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols | Mahesh Wagh, Debendra Das Sharma | 2025-02-11 |
| 12189470 | Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects | Debendra Das Sharma | 2025-01-07 |