DS

Debendra Das Sharma

IN Intel: 23 patents #15 of 3,896Top 1%
📍 Saratoga, CA: #4 of 487 inventorsTop 1%
🗺 California: #224 of 55,090 inventorsTop 1%
Overall (2025): #1,206 of 469,880Top 1%
23
Patents 2025

Issued Patents 2025

Showing 1–23 of 23 patents

Patent #TitleCo-InventorsDate
12405912 Link initialization training and bring up for die-to-die interconnect Narasimha Lanka, Lakshmipriya Seshan, Swadesh Choudhary, Zuoguo Wu, Gerald Pasdast 2025-09-02
12399832 Shared buffered memory routing Michelle C. Jen, Brian S. Morris 2025-08-26
12373279 Selection of processing mode for receiver circuit Swadesh Choudhary, Michelle C. Jen 2025-07-29
12360934 Parameter exchange for a die-to-die interconnect Mahesh S. Natu, Sridhar Muthrasanallur, Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan 2025-07-15
12362306 Clock-gating in die-to-die (D2D) interconnects Narasimha Lanka, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu, Swadesh Choudhary 2025-07-15
12353305 Compliance and debug testing of a die-to-die interconnect Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast 2025-07-08
12353329 System, apparatus and methods for direct data reads from memory Robert G. Blankenship 2025-07-08
12355565 Low-latency forward error correction for high-speed serial links 2025-07-08
12332752 Hardware logging for lane margining and characterization Michelle C. Jen, Swadesh Choudhary, Raghucharan Boddupalli 2025-06-17
12332826 Die-to-die interconnect Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu 2025-06-17
12321305 Sideband interface for die-to-die interconnects Narasimha Lanka, Swadesh Choudhary, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast 2025-06-03
12316343 PHY-based retry techniques for die-to-die interfaces Narasimha Lanka, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast 2025-05-27
12316446 Latency optimization in partial width link states 2025-05-27
12259835 Disaggregation of computing devices using enhanced retimers with circuit switching 2025-03-25
12242336 Multi-protocol support on common physical layer 2025-03-04
12244326 Encoder and decoder of forward error correction (FEC) codec Swadesh Choudhary 2025-03-04
12222881 Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols Swadesh Choudhary, Mahesh Wagh 2025-02-11
12223358 Connecting accelerator resources using a switch Anil Rao 2025-02-11
12216607 Source ordering in device interconnects 2025-02-04
12219038 Alternate protocol negotiation in a high performance interconnect 2025-02-04
12197357 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more 2025-01-14
12189470 Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects Swadesh Choudhary 2025-01-07
12189550 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more 2025-01-07