| 12419085 |
Integrated circuit structures having backside gate tie-down |
Leonard P. GULER, Mauro J. Kobrinsky, Mohit K. HARAN, Marni Nabors, Tahir Ghani +2 more |
2025-09-16 |
| 12405526 |
Extreme ultraviolet lithography patterning with assist features |
Leonard P. GULER, Tahir Ghani, Hossam A. Abdallah, Dario Farias, Tsuan-Chung CHANG +5 more |
2025-09-02 |
| 12408422 |
Integrated circuit structures with backside gate cut or trench contact cut |
Leonard P. GULER, Tahir Ghani |
2025-09-02 |
| 12400913 |
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication |
Manish Chandhok, Elijah V. Karpov, Mohit K. HARAN, Reken Patel, Gurpreet Singh +5 more |
2025-08-26 |
| 12382721 |
Integrated circuit structures having cut metal gates with dielectric spacer fill |
Leonard P. GULER, Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka +5 more |
2025-08-05 |
| 12364001 |
Integrated circuit structures with backside gate partial cut or trench contact partial cut |
Leonard P. GULER, Mohammad HASAN, Tahir Ghani |
2025-07-15 |
| 12308284 |
Plug and trench architectures for integrated circuits and methods of manufacture |
Marvin Young Paik, Hyunsoo Park, Mohit K. HARAN, Alexander F. Kaplan, Ruth A. Brain |
2025-05-20 |
| 12293913 |
Directed self-assembly enabled subtractive metal patterning |
Gurpreet Singh, Richard E. Schenker, Nityan NAIR, Nafees Kabir, Gauri Nabar +7 more |
2025-05-06 |
| 12278204 |
Pattern decomposition lithography techniques |
Hossam A. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood |
2025-04-15 |
| 12266708 |
Integrated circuit structures having dielectric anchor void |
Leonard P. GULER, Tahir Ghani |
2025-04-01 |
| 12266527 |
Directed self-assembly enabled patterning over metal layers using assisting features |
Gurpreet Singh, Nityan NAIR, Nafees Kabir, Eungnak Han, Xuanxuan Chen +6 more |
2025-04-01 |
| 12249541 |
Vertical edge blocking (VEB) technique for increasing patterning process margin |
Leonard P. GULER, Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan |
2025-03-11 |
| 12249577 |
Cap structure for interconnect dielectrics and methods of fabrication |
Shashi Vyas, Sudipto Naskar |
2025-03-11 |
| 12237388 |
Transistor arrangements with stacked trench contacts and gate straps |
Andy Wei, Changyok Park, Guillaume Bouche, Hyuk-Ju Ryu, Mohit K. HARAN |
2025-02-25 |
| 12237223 |
Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication |
Paul A. Nyhus, Manish Chandhok, Mohit K. HARAN, Gurpreet Singh, Eungnak Han +5 more |
2025-02-25 |
| 12218052 |
Advanced lithography and self-assembled devices |
Richard E. Schenker, Robert L. Bristol, Kevin Lin, Florian Gstrein, James M. Blackwell +6 more |
2025-02-04 |
| 12199161 |
Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication |
Mohit K. HARAN, Andy Wei |
2025-01-14 |