| 12426316 |
Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material |
Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar, Tahir Ghani |
2025-09-23 |
| 12419085 |
Integrated circuit structures having backside gate tie-down |
Mauro J. Kobrinsky, Mohit K. HARAN, Marni Nabors, Tahir Ghani, Charles H. Wallace +2 more |
2025-09-16 |
| 12408422 |
Integrated circuit structures with backside gate cut or trench contact cut |
Charles H. Wallace, Tahir Ghani |
2025-09-02 |
| 12405526 |
Extreme ultraviolet lithography patterning with assist features |
Tahir Ghani, Charles H. Wallace, Hossam A. Abdallah, Dario Farias, Tsuan-Chung CHANG +5 more |
2025-09-02 |
| 12400913 |
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication |
Manish Chandhok, Elijah V. Karpov, Mohit K. HARAN, Reken Patel, Charles H. Wallace +5 more |
2025-08-26 |
| 12382706 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices |
Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani |
2025-08-05 |
| 12382721 |
Integrated circuit structures having cut metal gates with dielectric spacer fill |
Chanaka D. Munasinghe, Makram ABD EL QADER, Marie T. Conte, Saurabh Morarka, Elliot N. Tan +5 more |
2025-08-05 |
| 12369392 |
Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates |
Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more |
2025-07-22 |
| 12369393 |
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach |
Dax M. Crum, Biswajeet Guha, Tahir Ghani |
2025-07-22 |
| 12364002 |
Integrated circuit structures having metal gates with tapered plugs |
Mohammad HASAN, Biswajeet Guha, Oleg Golonzka, Leah Shoer, Daniel G. Ouellette +2 more |
2025-07-15 |
| 12364001 |
Integrated circuit structures with backside gate partial cut or trench contact partial cut |
Mohammad HASAN, Charles H. Wallace, Tahir Ghani |
2025-07-15 |
| 12349394 |
Dielectric isolation layer between a nanowire transistor and a substrate |
Bruce Beattie, Biswajeet Guha, Jun Sung Kang, William Hsu |
2025-07-01 |
| 12342612 |
Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions |
Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar |
2025-06-24 |
| 12328905 |
Cavity spacer for nanowire transistors |
William Hsu, Biswajeet Guha, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more |
2025-06-10 |
| 12272688 |
Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap |
Zachary Geiger, Glenn A. Glass, Szuya S. Liao |
2025-04-08 |
| 12266708 |
Integrated circuit structures having dielectric anchor void |
Charles H. Wallace, Tahir Ghani |
2025-04-01 |
| 12249541 |
Vertical edge blocking (VEB) technique for increasing patterning process margin |
Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace |
2025-03-11 |
| 12224350 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices |
Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani |
2025-02-11 |
| 12211925 |
Gate-all-around integrated circuit structures having oxide sub-fins |
Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar |
2025-01-28 |