Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426316 | Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Leonard P. GULER, Biswajeet Guha, Swaminathan Sivakumar, Tahir Ghani | 2025-09-23 |