Issued Patents 2025
Showing 1–25 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431408 | TSV and backside power distribution structure | Mukta G. Farooq | 2025-09-30 |
| 12432968 | Nanowire source/drain formation for nanosheet device | Julien Frougier, Kangguo Cheng, Alexander Reznicek | 2025-09-30 |
| 12432960 | Wraparound contact with reduced distance to channel | Reinaldo Vega, Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker, Pietro Montanini +2 more | 2025-09-30 |
| 12426314 | Strain generation and anchoring in gate-all-around field effect transistors | Julien Frougier, Sung-Dae Suk, Kangguo Cheng, Andrew M. Greene | 2025-09-23 |
| 12426338 | Buried power rail with robust connection to a wrap around contact | Kangguo Cheng, Julien Frougier, Chanro Park | 2025-09-23 |
| 12424539 | Local enlarged via-to-backside power rail | Albert M. Chu, Carl Radens, Brent A. Anderson | 2025-09-23 |
| 12424591 | Method and structure of forming independent contact for staggered CFET | Albert M. Chu, Albert M. Young, Brent A. Anderson, Junli Wang, Ravikumar Ramachandran | 2025-09-23 |
| 12424549 | Skip-level TSV with hybrid dielectric scheme for backside power delivery | Nicholas Anthony Lanzillo, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger | 2025-09-23 |
| 12424557 | Dual structured buried rail | Huai Huang, Nicholas Anthony Lanzillo, Hosadurga Shobha, Lawrence A. Clevenger | 2025-09-23 |
| 12419079 | Field effect transistor with backside source/drain | Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Su Chen Fan, Shogo Mochizuki +1 more | 2025-09-16 |
| 12419080 | Semiconductor structure with wrapped-around backside contact | Chanro Park, Min Gyu Sung, Kangguo Cheng, Julien Frougier | 2025-09-16 |
| 12417963 | Isolation rail between backside power rails | Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Hosadurga Shobha, Baozhen Li | 2025-09-16 |
| 12417944 | Formation of trench silicide source or drain contacts without gate damage | Andrew M. Greene, Laertis Economikos, Veeraraghavan S. Basker, Chanro Park, Hui Zang | 2025-09-16 |
| 12419024 | High density static random-access memory | Brent A. Anderson, Albert M. Chu, Carl Radens | 2025-09-16 |
| 12417979 | Pass-through wiring in notched interconnect | Nicholas Anthony Lanzillo, Albert M. Chu, Reinaldo Vega, Lawrence A. Clevenger, Brent A. Anderson | 2025-09-16 |
| 12417974 | Decoupling capacitance in backside interconnect | Rajiv V. Joshi, Nicholas Anthony Lanzillo | 2025-09-16 |
| 12412830 | Semiconductor device with power via | Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega, Lawrence A. Clevenger +2 more | 2025-09-09 |
| 12414328 | Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors | Huimei Zhou, Julien Frougier, Nicolas Loubet, Miaomiao Wang, Veeraraghavan S. Basker | 2025-09-09 |
| 12412836 | Backside power plane | Nicholas Anthony Lanzillo, Hosadurga Shobha, Lawrence A. Clevenger, Huai Huang | 2025-09-09 |
| 12412829 | Method and structure of forming sidewall contact for stacked FET | Julien Frougier, Su Chen Fan, Ravikumar Ramachandran, Oleg Gluschenkov | 2025-09-09 |
| 12414336 | Semiconductor structure having stacked power rails | Huimei Zhou, Julien Frougier, Miaomiao Wang | 2025-09-09 |
| 12406930 | Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure | Stuart A. Sieg, Kevin S. Petrarca, Eric R. Miller | 2025-09-02 |
| 12402408 | Stacked FETS including devices with thick gate oxide | Julien Frougier, Nicolas Loubet, Junli Wang, Ruqiang Bao, Min Gyu Sung +2 more | 2025-08-26 |
| 12400960 | Vertical-transport field-effect transistor with backside gate contact | Brent A. Anderson, Albert M. Chu, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Reinaldo Vega | 2025-08-26 |
| 12402342 | Nanosheet device with T-shaped dual inner spacer | Pouya Hashemi, Alexander Reznicek, Takashi Ando | 2025-08-26 |