Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12419080 | Semiconductor structure with wrapped-around backside contact | Ruilong Xie, Chanro Park, Kangguo Cheng, Julien Frougier | 2025-09-16 |
| 12402408 | Stacked FETS including devices with thick gate oxide | Ruilong Xie, Julien Frougier, Nicolas Loubet, Junli Wang, Ruqiang Bao +2 more | 2025-08-26 |
| 12396227 | Full wrap around backside contact | Ruilong Xie, Kisik Choi, Junli Wang, Julien Frougier | 2025-08-19 |
| 12389609 | Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers | Julien Frougier, Ruilong Xie, Kangguo Cheng, Heng Wu, Chanro Park | 2025-08-12 |
| 12362004 | Scaled 2T DRAM | Julien Frougier, Ruilong Xie, Chanro Park, Juntao Li | 2025-07-15 |
| 12324197 | Spin-based gate-all-around transistors | Julien Frougier, Kangguo Cheng, Ruilong Xie, Chanro Park, Andrew Gaul | 2025-06-03 |
| 12317514 | Resistive random-access memory structures with stacked transistors | Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park, Soon-Cheon Seo | 2025-05-27 |
| 12310064 | Isolation pillar structures for stacked device structures | Ruilong Xie, Julien Frougier, Kangguo Cheng, Chanro Park | 2025-05-20 |