| 11848259 |
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages |
Dae-Woo Kim |
2023-12-19 |
| 11824008 |
Multi-chip package and method of providing die-to-die interconnects in same |
Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz +1 more |
2023-11-21 |
| 11798865 |
Nested architectures for enhanced heterogeneous integration |
Ravindranath V. Mahajan, Debendra Mallik, Digvijay A. Raorane |
2023-10-24 |
| 11784150 |
Rounded metal trace corner for stress reduction |
Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks |
2023-10-10 |
| 11742261 |
Nested architectures for enhanced heterogeneous integration |
Ravindranath V. Mahajan, Debendra Mallik, Digvijay A. Raorane |
2023-08-29 |
| 11728294 |
Capacitor die embedded in package substrate for providing capacitance to surface mounted die |
Andrew Collins, Jianyong Xie |
2023-08-15 |
| 11694952 |
Horizontal pitch translation using embedded bridge dies |
Kemal Aygun, Zhiguo Qian, Yidnekachew S. Mekonnen, Zhichao Zhang, Jianyong Xie |
2023-07-04 |
| 11676889 |
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages |
Arnab Sarkar, Dae-Woo Kim |
2023-06-13 |
| 11626372 |
Metal-free frame design for silicon bridges for semiconductor packages |
Dae-Woo Kim, Sairam Agraharam |
2023-04-11 |
| 11621223 |
Interconnect hub for dies |
Andrew Collins, Jianyong Xie |
2023-04-04 |
| 11569173 |
Bridge hub tiling architecture |
Andrew Collins, Digvijay A. Raorane, Wilfred Gomes, Ravindranath V. Mahajan |
2023-01-31 |