Issued Patents 2022
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532517 | Localized etch stop layer | Yun Han, Andrew Metz, Xinghua Sun, David L. O'Meara, Henan Zhang +1 more | 2022-12-20 |
| 11456212 | Platform and method of operating for integrated end-to-end fully self-aligned interconnect process | Robert D. Clark, Kai-Hung Yu | 2022-09-27 |
| 11444082 | Semiconductor apparatus having stacked gates and method of manufacture thereof | Jeffrey Smith, Anton J. deVilliers, Subhadeep Kal, Gerrit J. Leusink | 2022-09-13 |
| 11443953 | Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning | Anton J. deVilliers, Gerrit J. Leusink | 2022-09-13 |
| 11443949 | Method of selectively forming metal silicides for semiconductor devices | — | 2022-09-13 |
| 11398379 | Platform and method of operating for integrated end-to-end self-aligned multi-patterning process | Robert D. Clark, Richard A. Farrell, Angelique Raley, Sophie Thibaut | 2022-07-26 |
| 11374101 | Dual metal wrap-around contacts for semiconductor devices | Hiroaki Niimi, Takahiro Hakamata | 2022-06-28 |
| 11335599 | Self-aligned contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2022-05-17 |
| 11322401 | Reverse contact and silicide process for three-dimensional semiconductor devices | Jeffrey Smith, Lars Liebmann, Daniel Chanemougame, Hiroki Niimi, Subhadeep Kal +2 more | 2022-05-03 |
| 11302588 | Platform and method of operating for integrated end-to-end area-selective deposition process | Robert D. Clark, Jason Mehigan | 2022-04-12 |
| 11264254 | Substrate processing tool with integrated metrology and method of using | Robert D. Clark | 2022-03-01 |
| 11264289 | Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks | Jeffrey Smith, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more | 2022-03-01 |
| 11264274 | Reverse contact and silicide process for three-dimensional logic devices | Jeffrey Smith, Hiroaki Niimi, Jodi Grzeskowiak, Daniel Chanemougame, Lars Liebmann +2 more | 2022-03-01 |
| 11251077 | Method of forming a semiconductor device with air gaps for low capacitance interconnects | — | 2022-02-15 |
| 11251200 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2022-02-15 |
| 11217583 | Architecture design of monolithically integrated 3D CMOS logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2022-01-04 |