| 11527545 |
Architecture design and process for 3D logic and 3D memory |
H. Jim Fulford |
2022-12-13 |
| 11521972 |
High performance multi-dimensional device and logic integration |
H. Jim Fulford |
2022-12-06 |
| 11515306 |
Unified architectural design for enhanced 3D circuit options |
H. Jim Fulford |
2022-11-29 |
| 11508625 |
Method of making a continuous channel between 3D CMOS |
H. Jim Fulford |
2022-11-22 |
| 11410888 |
Method of making 3D CMOS with integrated channel and S/D regions |
H. Jim Fulford |
2022-08-09 |
| 11410992 |
3D semiconductor apparatus manufactured with a cantilever structure and method of manufacture thereof |
H. Jim Fulford |
2022-08-09 |
| 11393813 |
Method of architecture design for enhanced 3D device performance |
H. Jim Fulford |
2022-07-19 |
| 11362091 |
Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance |
H. Jim Fulford |
2022-06-14 |
| 11342339 |
Method of making six transistor SRAM cell using connections between 3D transistor stacks |
H. Jim Fulford |
2022-05-24 |
| 11302587 |
Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices |
H. Jim Fulford |
2022-04-12 |
| 11282828 |
High density architecture design for 3D logic and 3D memory circuits |
H. Jim Fulford |
2022-03-22 |
| 11276704 |
Device and method of forming with three-dimensional memory and three-dimensional logic |
H. Jim Fulford |
2022-03-15 |
| 11264285 |
Method for forming film stacks with multiple planes of transistors having different transistor architectures |
Jim Fulford |
2022-03-01 |
| 11264289 |
Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks |
Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, H. Jim Fulford +1 more |
2022-03-01 |
| 11251080 |
Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits |
H. Jim Fulford, Anton J. deVilliers |
2022-02-15 |
| 11251159 |
High performance CMOS using 3D device layout |
H. Jim Fulford |
2022-02-15 |
| 11222964 |
Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits |
H. Jim Fulford |
2022-01-11 |