Issued Patents 2022
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11531486 | Migrating data from a large extent pool to a small extent pool | Hui Zhang, Clint A. Hardy, Karl A. Nielsen, Qiang Xie | 2022-12-20 |
| 11494304 | Indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache | Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson | 2022-11-08 |
| 11442649 | Migrating data from a large extent pool to a small extent pool | Hui Zhang, Clint A. Hardy, Karl A. Nielsen, Qiang Xie | 2022-09-13 |
| 11379329 | Validation of data written via two different bus interfaces to a dual server based storage controller | Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta | 2022-07-05 |
| 11321123 | Determining an optimum number of threads to make available per core in a multi-core processor complex to executive tasks | Brian A. Rinaldi, Lokesh M. Gupta, Kevin J. Ash, Trung N. Nguyen, Clint A. Hardy +1 more | 2022-05-03 |
| 11321234 | Using a mirroring cache list to demote modified tracks from cache | Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson | 2022-05-03 |
| 11321201 | Using a mirroring cache list to mirror modified tracks | Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson | 2022-05-03 |
| 11314435 | Converting small extent storage pools into large extent storage pools in place | Clint A. Hardy, Karl A. Nielsen | 2022-04-26 |
| 11314659 | Using real segments and alternate segments in non-volatile storage | Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta | 2022-04-26 |
| 11294812 | Obtaining cache resources for expected writes to tracks in a write set after the cache resources were released for the tracks in the write set | Beth A. Peterson, Chung Man Fung, Matthew R. Craig | 2022-04-05 |
| 11281593 | Using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors | Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash | 2022-03-22 |
| 11281502 | Dispatching tasks on processors based on memory access efficiency | Lokesh M. Gupta, Kevin J. Ash, Trung N. Nguyen | 2022-03-22 |
| 11281380 | Management of data written via a bus interface to a storage controller during consistent copying of data | Matthew J. Ward, Joshua J. Crawford, Carol S. Mellgren, Matthew R. Craig | 2022-03-22 |
| 11263097 | Using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache | Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Beth A. Peterson | 2022-03-01 |
| 11243885 | Providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track | Beth A. Peterson, Chung Man Fung, Warren K. Stanley, Matthew J. Ward | 2022-02-08 |
| 11231998 | Generating a chain of a plurality of write requests | Jeffrey A. Berger, Susan K. Candelaria, Beth A. Peterson, Harry M. Yudenfriend | 2022-01-25 |
| 11226899 | Populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node | Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Brian A. Rinaldi | 2022-01-18 |