Issued Patents 2020
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672776 | Memory circuit having resistive device coupled with supply voltage line | Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang | 2020-06-02 |
| 10665595 | Metal isolation testing in the context of memory cells | Te-Hsin Chiu, Meng-Han Lin | 2020-05-26 |
| 10665600 | Memory devices and method of fabricating same | Chang-Ming Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai | 2020-05-26 |
| 10663512 | Testing of semiconductor chips with microbumps | Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang | 2020-05-26 |
| 10658373 | Method for manufacturing semiconductor device with metal gate memory device and metal gate logic device | Harry-Hak-Lay Chuang, Ya-Chen Kao | 2020-05-19 |
| 10650882 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Kao-Cheng Lin, Yen-Huei Chen | 2020-05-12 |
| 10644013 | Cell boundary structure for embedded memory | Meng-Han Lin, Chih-Ren Hsieh, Chih-Pin Huang | 2020-05-05 |
| 10629537 | Conductive vias in semiconductor packages and methods of forming same | Cheng-Hsien Hsieh, Li-Han Hsu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu +1 more | 2020-04-21 |
| 10553580 | Method of manufacturing semiconductor device | Harry-Hak-Lay Chuang | 2020-02-04 |
| 10535675 | High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory | Harry-Hak-Lay Chuang, Ya-Chen Kao, Yi Hsien Lu | 2020-01-14 |