Issued Patents 2020
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878894 | Memory device having low bitline voltage swing in read port and method for reading memory cell | Hidehiro Fujiwara, Haruki Mori, Chih-Yu Lin | 2020-12-29 |
| 10872644 | Boost bypass circuitry in a memory storage device | Hidehiro Fujiwara | 2020-12-22 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Sahil Preet Singh | 2020-12-01 |
| 10847214 | Low voltage bit-cell | Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Ting Lin | 2020-11-24 |
| 10839894 | Memory computation circuit and method | Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-11-17 |
| 10832765 | Variation tolerant read assist circuit for SRAM | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Sahil Preet Singh | 2020-11-10 |
| 10803928 | Low voltage memory device | Mahmut Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-10-13 |
| 10790015 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Sahil Preet Singh, Jung-Hsuan Chen, Avinash Chander, Albert Ying | 2020-09-29 |
| 10783955 | Memory circuit having shared word line | Hidehiro Fujiwara, Li-Wen Wang, Hung-Jen Liao | 2020-09-22 |
| 10783954 | Semiconductor memory with respective power voltages for memory cells | Wei-Cheng Wu, Chih-Yu Lin, Kao-Cheng Lin, Wei Min Chan | 2020-09-22 |
| 10770131 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Mahmut Sinangil | 2020-09-08 |
| 10770134 | SRAM based authentication circuit | Chien-Chen Lin, Wei Min Chan, Chih-Yu Lin, Shih-Lien Linus Lu | 2020-09-08 |
| 10755768 | Semiconductor device including distributed write driving arrangement and method of operating same | Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang | 2020-08-25 |
| 10734066 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Hung-Jen Liao | 2020-08-04 |
| 10714181 | Memory cell | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Chien-Chen Lin | 2020-07-14 |
| 10685704 | Static random access memory circuit | Wei-Cheng Wu, Wei Min Chan, Hung-Jen Liao, Ping-Wei Wang | 2020-06-16 |
| 10672776 | Memory circuit having resistive device coupled with supply voltage line | Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu | 2020-06-02 |
| 10651114 | Apparatus and method of three dimensional conductive lines | Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang | 2020-05-12 |
| 10650882 | Static random access memory with a supplementary driver circuit and method of controlling the same | Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin | 2020-05-12 |
| 10636458 | Sense amplifier layout for FinFET technology | Chien-Chi TIEN, Kao-Cheng Lin, Jung-Hsuan Chen | 2020-04-28 |
| 10559333 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2020-02-11 |
| 10541007 | Memory device with strap cells | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw | 2020-01-21 |
| 10535658 | Memory device with reduced-resistance interconnect | Sahil Preet Singh | 2020-01-14 |
| 10529415 | Write assist for a memory device and methods of forming the same | Sahil Preet Singh, Hung-Jen Liao | 2020-01-07 |