Issued Patents 2020
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878894 | Memory device having low bitline voltage swing in read port and method for reading memory cell | Haruki Mori, Chih-Yu Lin, Yen-Huei Chen | 2020-12-29 |
| 10872644 | Boost bypass circuitry in a memory storage device | Yen-Huei Chen | 2020-12-22 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2020-12-01 |
| 10839894 | Memory computation circuit and method | Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-11-17 |
| 10832765 | Variation tolerant read assist circuit for SRAM | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh | 2020-11-10 |
| 10783955 | Memory circuit having shared word line | Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao | 2020-09-22 |
| 10770131 | SRAM cell for interleaved wordline scheme | Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2020-09-08 |
| 10755768 | Semiconductor device including distributed write driving arrangement and method of operating same | Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2020-08-25 |
| 10734066 | Static random access memory with write assist circuit | Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2020-08-04 |
| 10714181 | Memory cell | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2020-07-14 |
| 10706934 | Failure detection circuitry for address decoder for a data storage device | Ching-Wei Wu | 2020-07-07 |
| 10580484 | Semiconductor integrated circuit device | Makoto Yabuuchi | 2020-03-03 |
| 10553300 | Method of detecting address decoding error and address decoder error detection system | Ching-Wei Wu, Chun-Hao Chang | 2020-02-04 |