Issued Patents 2020
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879115 | Semiconductor device and forming method thereof | Ming-Han Lee, Shih-Kang Fu, Meng-Pei Lu | 2020-12-29 |
| 10867913 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Tien-I Bao | 2020-12-15 |
| 10867850 | Selective deposition method for forming semiconductor structure | Cheng-Chin Lee, Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen | 2020-12-15 |
| 10861742 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2020-12-08 |
| 10818509 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2020-10-27 |
| 10784160 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao | 2020-09-22 |
| 10763211 | Semiconductor device and manufacturing method thereof | Ming-Han Lee | 2020-09-01 |
| 10714424 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Tz-Jun Kuo | 2020-07-14 |
| 10676351 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Carlos H. Diaz, Ken-Ichi Goto, Tai-I Yang | 2020-06-09 |
| 10665467 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2020-05-26 |
| 10651279 | Semiconductor interconnect structure having graphene-capped metal interconnects | Shin-Yi Yang, Ching-Fu Yeh, Ming-Han Lee | 2020-05-12 |
| 10622453 | Vertical MOS transistor | Tai-I Yang, Yung-Chih Wang, Shin-Yi Yang, Chih Wei Lu, Hsin-Ping Chen | 2020-04-14 |
| 10534273 | Multi-metal fill with self-aligned patterning and dielectric with voids | Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Li-Lin Su, Yung-Hsu Wu | 2020-01-14 |
| 10535559 | Semiconductor interconnect structure having a graphene barrier layer | Shin-Yi Yang, Ming-Han Lee | 2020-01-14 |