Issued Patents 2020
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10685937 | Integrated circuit package having dummy structures and method of forming same | Hsien-Wei Chen, Chen-Hua Yu | 2020-06-16 |
| 10685935 | Forming metal bonds with recesses | Hsien-Wei Chen, Sung-Feng Yeh, Wen-Chih Chiou | 2020-06-16 |
| 10685910 | Packages with Si-substrate-free interposer and method forming same | Chen-Hua Yu, Sung-Feng Yeh, Hsien-Wei Chen | 2020-06-16 |
| 10672754 | Semiconductor component, package structure and manufacturing method thereof | Hsien-Wei Chen, Sung-Feng Yeh, Chi-Hwang Tai | 2020-06-02 |
| 10672674 | Method of forming semiconductor device package having testing pads on a topmost die | Chen-Hua Yu, Sung-Feng Yeh, Hsien-Wei Chen, Hui Liu, Ching-Pin Yuan | 2020-06-02 |
| 10665582 | Method of manufacturing semiconductor package structure | Yi-Hsiu Chen, Chen-Hua Yu, Wen-Chih Chiou | 2020-05-26 |
| 10658333 | Package structure and method of fabricating the same | Hsien-Wei Chen, Sung-Feng Yeh | 2020-05-19 |
| 10651149 | Packages formed using RDL—last process | Chen-Hua Yu | 2020-05-12 |
| 10622327 | Method for manufacturing semiconductor structure | Chen-Hua Yu, Sung-Feng Yeh | 2020-04-14 |
| 10541228 | Packages formed using RDL-last process | Chen-Hua Yu | 2020-01-21 |
| 10541227 | System on integrated chips and methods of forming same | Sung-Feng Yeh, Chen-Hua Yu | 2020-01-21 |
| 10535636 | Integrating passive devices in package structures | Chih-Chia Hu | 2020-01-14 |
| 10535631 | 3D Chip-on-wager-on-substrate structure with via last process | Chen-Hua Yu, Wen-Ching Tsai, Sung-Feng Yeh | 2020-01-14 |