Issued Patents 2020
Showing 76–98 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10586800 | Anti-fuse with reduced programming voltage | Kangguo Cheng, Chengwen Pei, Geng Wang | 2020-03-10 |
| 10580770 | Vertical transistors with different gate lengths | Xin Miao, Chen Zhang, Kangguo Cheng | 2020-03-03 |
| 10573561 | Formation of stacked nanosheet semiconductor devices | Kangguo Cheng, Heng Wu, Peng Xu | 2020-02-25 |
| 10564125 | Self-aligned nanotips with tapered vertical sidewalls | Kangguo Cheng, Peng Xu, Heng Wu | 2020-02-18 |
| 10566251 | Techniques for forming vertical transport FET | Choonghyun Lee, Kangguo Cheng | 2020-02-18 |
| 10559625 | RRAM cells in crossbar array architecture | Dexin Kong, Takashi Ando, Kangguo Cheng | 2020-02-11 |
| 10559685 | Vertical field effect transistor with reduced external resistance | Kangguo Cheng, Choonghyun Lee, Peng Xu | 2020-02-11 |
| 10559675 | Stacked silicon nanotubes | Kangguo Cheng, Choonghyun Lee, Peng Xu | 2020-02-11 |
| 10559662 | Hybrid aspect ratio trapping | Kangguo Cheng, Ramachandra Divakaruni, Hong He | 2020-02-11 |
| 10559566 | Reduction of multi-threshold voltage patterning damage in nanosheet device structure | Choonghyun Lee, Kangguo Cheng, Shogo Mochizuki | 2020-02-11 |
| 10553354 | Method of manufacturing inductor with ferromagnetic cores | Kangguo Cheng, Geng Wang, Qintao Zhang | 2020-02-04 |
| 10553535 | Formation of semiconductor devices including electrically programmable fuses | Chih-Chao Yang | 2020-02-04 |
| 10553495 | Nanosheet transistors with different gate dielectrics and workfunction metals | Kangguo Cheng, Choonghyun Lee, Peng Xu | 2020-02-04 |
| 10553445 | Stacked nanowires | Zhenxing Bi, Kangguo Cheng, Xin Miao | 2020-02-04 |
| 10544042 | Nanoparticle structure and process for manufacture | Qing Cao, Kangguo Cheng | 2020-01-28 |
| 10541176 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Kangguo Cheng, Peng Xu | 2020-01-21 |
| 10541177 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Devendra K. Sadana | 2020-01-21 |
| 10541128 | Method for making VFET devices with ILD protection | Zhenxing Bi, Kangguo Cheng, Peng Xu | 2020-01-21 |
| 10535755 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Kangguo Cheng, Peng Xu | 2020-01-14 |
| 10535733 | Method of forming a nanosheet transistor | Kangguo Cheng, Choonghyun Lee, Peng Xu | 2020-01-14 |
| 10535754 | Method and structure for forming a vertical field-effect transistor | Peng Xu, Choonghyun Lee, Kangguo Cheng | 2020-01-14 |
| 10529851 | Forming bottom source and drain extension on vertical transport FET (VTFET) | Shogo Mochizuki, Kangguo Cheng, Choonghyun Lee | 2020-01-07 |
| 10529829 | Silicon germanium alloy fins with reduced defects | Kangguo Cheng, Hong He | 2020-01-07 |