Issued Patents 2019
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522654 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Lars Liebmann | 2019-12-31 |
| 10418277 | Air gap spacer formation for nano-scale semiconductor devices | Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Son V. Nguyen +2 more | 2019-09-17 |
| 10366988 | Selective contact etch for unmerged epitaxial source/drain regions | Alexander Reznicek | 2019-07-30 |
| 10355109 | Spacer formation on semiconductor device | Thamarai S. Devarajan, Eric R. Miller, Soon-Cheon Seo | 2019-07-16 |
| 10332977 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Lars Liebmann | 2019-06-25 |
| 10304936 | Protection of high-K dielectric during reliability anneal on nanosheet structures | Nicolas Loubet, Vijay Narayanan, Muthumanickam Sankarapandian | 2019-05-28 |
| 10269652 | Vertical transistor top epitaxy source/drain and contact structure | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2019-04-23 |
| 10262904 | Vertical transistor top epitaxy source/drain and contact structure | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2019-04-16 |
| 10256320 | Vertical field-effect-transistors having a silicon oxide layer with controlled thickness | Chi-Chun Liu, Luciana Meli, Muthumanickam Sankarapandian, Kristin Schmidt, Ankit Vora | 2019-04-09 |
| 10236360 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek | 2019-03-19 |
| 10229982 | Pure boron for silicide contact | Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita | 2019-03-12 |
| 10170479 | Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors | Kangguo Cheng, Zuoguang Liu, Tenko Yamashita | 2019-01-01 |