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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Patrick Morrow — 15 Patents in 2019

Intel: 15 patents #101 of 5,769Top 2%
Portland, OR: #39 of 1,929 inventorsTop 3%
Oregon: #65 of 4,620 inventorsTop 2%
Overall (2019): #3,664 of 560,194Top 1%
15 Patents 2019

Issued Patents 2019

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10522510 Heterogeneous integration of ultrathin functional block by solid phase adhesive and selective transfer Kimin Jun, Jacob Jensen, Paul B. Fischer 2019-12-31 $25,528,000
10490542 Integrated circuit layout using library cells with alternating conductive lines Donald W. Nelson, Steven M. Burns 2019-11-26 $25,149,000
10490449 Techniques for revealing a backside of an integrated circuit device, and associated configurations Il-Seok Son, Colin T. Carver, Paul B. Fischer, Kimin Jun 2019-11-26 $25,149,000
10483321 High density memory architecture using back side metal layers Yih Wang 2019-11-19 $26,843,000
10468489 Isolation structures for an integrated circuit element and method of making same Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Kerryann Marrietta Foley, Stephen M. Cea +1 more 2019-11-05 $22,190,000
10453679 Methods and devices integrating III-N transistor circuitry with Si transistor circuitry Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun +3 more 2019-10-22 $16,310,000
10439057 Multi-gate high electron mobility transistors and methods of fabrication Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander 2019-10-08 $19,521,000
10396045 Metal on both sides of the transistor integrated with magnetic inductors Paul B. Fischer 2019-08-27 $17,353,000
10367070 Methods of forming backside self-aligned vias and structures formed thereby Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer 2019-07-30 $29,864,000
10361090 Vertical channel transistors fabrication process by selective subtraction of a regular grid Kimin Jun, Donald W. Nelson 2019-07-23 $32,139,000
10325840 Metal on both sides with power distributed through the silicon Donald W. Nelson, Mark Bohr 2019-06-18 $21,210,000
10304946 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Rishabh Mehandru, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more 2019-05-28 $17,387,000
10297592 Monolithic three-dimensional (3D) ICs with local inter-level interconnects Kimin Jun, M. Clair Webb, Donald W. Nelson 2019-05-21 $20,944,000
10236282 Partial layer transfer system and method Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer 2019-03-19 $29,538,000
10186484 Metal on both sides with clock gated-power and signal routing underneath Donald W. Nelson, Kimin Jun 2019-01-22 $27,645,000