Issued Patents 2019
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497781 | Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices | Aaron D. Lilak, Rishabh Mehandru, Cory E. Weber | 2019-12-03 |
| 10483385 | Nanowire structures having wrap-around contacts | Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael Haverty, Sadasivan Shankar | 2019-11-19 |
| 10468489 | Isolation structures for an integrated circuit element and method of making same | Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Patrick Morrow, Kerryann Marrietta Foley +1 more | 2019-11-05 |
| 10453967 | Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device | Rishabh Mehandru, Szuya S. Liao | 2019-10-22 |
| 10411090 | Hybrid trigate and nanowire CMOS device architecture | Cory E. Weber, Rishabh Mehandru | 2019-09-10 |
| 10403752 | Prevention of subchannel leakage current in a semiconductor device with a fin structure | Karthik Jambunathan, Glenn A. Glass, Chandra S. Mohapatra, Anand S. Murthy, Tahir Ghani | 2019-09-03 |
| 10304929 | Two-dimensional condensation for uniaxially strained semiconductor fins | Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn | 2019-05-28 |
| 10304946 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim +1 more | 2019-05-28 |