Issued Patents 2018
Showing 1–25 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164110 | Finfet including improved epitaxial topology | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-12-25 |
| 10134903 | Vertical slit transistor with optimized AC performance | Qing Liu, Xiuyu Cai, Ruilong Xie | 2018-11-20 |
| 10134472 | Floating gate architecture for deep neural network application | Effendi Leobandung, Yulong Li, Paul M. Solomon | 2018-11-20 |
| 10134840 | Series resistance reduction in vertically stacked silicon nanowire transistors | Xiuyu Cai, Qing Liu, Ruilong Xie | 2018-11-20 |
| 10134864 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-11-20 |
| 10128335 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-11-13 |
| 10109723 | Punch through stopper in bulk FinFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-10-23 |
| 10103247 | Vertical transistor having buried contact, and contacts using work function metals and silicides | Ruilong Xie, Hui Zang, Kangguo Cheng, Tenko Yamashita | 2018-10-16 |
| 10103251 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-10-16 |
| 10096692 | Vertical field effect transistor with reduced parasitic capacitance | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-10-09 |
| 10096713 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui | 2018-10-09 |
| 10084070 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-09-25 |
| 10079234 | Metal-insulator-metal capacitor analog memory unit cell | Effendi Leobandung, Yulong Li, Paul M. Solomon | 2018-09-18 |
| 10079292 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-09-18 |
| 10062762 | Semiconductor devices having low contact resistance and low current leakage | Qing Liu, Xiuyu Cai, Ruilong Xie | 2018-08-28 |
| 10056378 | Silicon nitride fill for PC gap regions to increase cell density | Dechao Guo, Zuoguang Liu, Tenko Yamashita | 2018-08-21 |
| 10050107 | Nanosheet transistors on bulk material | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-08-14 |
| 10038076 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Hui Zang | 2018-07-31 |
| 10037919 | Integrated single-gated vertical field effect transistor (VFET) and independent double-gated VFET | Ruilong Xie, Kangguo Cheng, Tenko Yamashita | 2018-07-31 |
| 10037944 | Self-aligned contact process enabled by low temperature | Hong He, Chiahsun Tseng, Yunpeng Yin | 2018-07-31 |
| 10032677 | Method and structure to fabricate closely packed hybrid nanowires at scaled pitch | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-07-24 |
| 10020303 | Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer | Hong He, Shogo Mochizuki, Chiahsun Tseng, Yunpeng Yin | 2018-07-10 |
| 10020227 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Kangguo Cheng, Juntao Li | 2018-07-10 |
| 10014370 | Air gap adjacent a bottom source/drain region of vertical transistor device | Ruilong Xie, Kangguo Cheng, Tenko Yamashita | 2018-07-03 |
| 10008582 | Spacers for tight gate pitches in field effect transistors | Ruilong Xie | 2018-06-26 |