Issued Patents 2017
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9589857 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu +1 more | 2017-03-07 |
| 9583415 | Packages with thermal interface material on the sidewalls of stacked dies | Chen-Hua Yu, Wensen Hung, Szu-Po Huang, An-Jhih Su, Hsiang-Fan Lee +2 more | 2017-02-28 |
| 9581638 | Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages | Wei-Cheng Wu, Li-Han Hsu, Sao-Ling Chiu, Shang-Yun Hou, Chen-Hua Lin | 2017-02-28 |
| 9576938 | 3DIC packages with heat dissipation structures | Wensen Hung, Szu-Po Huang, Kim Hong Chen | 2017-02-21 |
| 9576926 | Pad structure design in fan-out package | Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen | 2017-02-21 |
| 9570366 | Passivation layer for packaged chip | Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu, Tzuan-Horng Liu, Tzu-Wei Chiu +1 more | 2017-02-14 |
| 9570324 | Method of manufacturing package system | Wei-Cheng Wu, Shang-Yun Hou, Chen-Hua Yu | 2017-02-14 |
| 9553053 | Bump structure for yield improvement | Tzu-Wei Chiu, Tzu-Yu Wang, Shang-Yun Hou, Hsien-Wei Chen, Hung-An Teng +1 more | 2017-01-24 |
| 9553000 | Interconnect structure for wafer level package | Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung | 2017-01-24 |