Issued Patents 2016
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530860 | III-V MOSFETs with halo-doped bottom barrier layer | Pranita Kerber, Chung-Hsun Lin, Amlan Majumdar | 2016-12-27 |
| 9530876 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin | 2016-12-27 |
| 9514937 | Tapered nanowire structure with reduced off current | Sarunya Bangsaruntip | 2016-12-06 |
| 9496338 | Wire-last gate-all-around nanowire FET | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2016-11-15 |
| 9496184 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Gen P. Lauer, Isaac Lauer | 2016-11-15 |
| 9483592 | Maintaining stress in a layout design of an integrated circuit having fin-type field-effect transistor devices | Karthik Balakrishnan, Pouya Hashemi, Tenko Yamashita | 2016-11-01 |
| 9472658 | III-V nanowire FET with compositionally-graded channel and wide-bandgap core | Anirban Basu, Guy M. Cohen, Amlan Majumdar | 2016-10-18 |
| 9466673 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Isaac Lauer, Alexander Reznicek | 2016-10-11 |
| 9449820 | Epitaxial growth techniques for reducing nanowire dimension and pitch | Guy M. Cohen, Michael A. Guillorn, Isaac Lauer | 2016-09-20 |
| 9443951 | Embedded planar source/drain stressors for a finFET including a plurality of fins | Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2016-09-13 |
| 9443949 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2016-09-13 |
| 9437443 | Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides | Markus Brink, Michael A. Guillorn, Sebastian U. Engelmann, Hiroyuki Miyazoe, Adam M. Pyzyna | 2016-09-06 |
| 9437613 | Multiple VT in III-V FETs | Josephine B. Chang, Isaac Lauer, Amlan Majumdar | 2016-09-06 |
| 9397199 | Methods of forming multi-Vt III-V TFET devices | Unoh Kwon, Siddarth A. Krishnan, Vijay Narayanan | 2016-07-19 |
| 9391163 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer | 2016-07-12 |
| 9390980 | III-V compound and germanium compound nanowire suspension with germanium-containing release layer | Guy M. Cohen, Isaac Lauer, Alexander Reznicek | 2016-07-12 |
| 9373638 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Gen P. Lauer, Isaac Lauer, Alexander Reznicek | 2016-06-21 |
| 9368574 | Nanowire field effect transistor with inner and outer gates | Anirban Basu, Guy M. Cohen, Amlan Majumdar | 2016-06-14 |
| 9368599 | Graphene/nanostructure FET with self-aligned contact and gate | Josephine B. Chang, Isaac Lauer | 2016-06-14 |
| 9362354 | Tuning gate lengths in semiconductor device structures | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer | 2016-06-07 |
| 9343142 | Nanowire floating gate transistor | Sarunya Bangsaruntip, Guy M. Cohen, Amlan Majumdar | 2016-05-17 |
| 9337309 | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels | Anirban Basu, Amlan Majumdar | 2016-05-10 |
| 9337255 | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels | Anirban Basu, Amlan Majumdar | 2016-05-10 |
| 9324801 | Nanowire FET with tensile channel stressor | Isaac Lauer, Chung-Hsun Lin | 2016-04-26 |
| 9299615 | Multiple VT in III-V FETs | Josephine B. Chang, Isaac Lauer, Amlan Majumdar | 2016-03-29 |